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...that Kleenex tissue was originally designed to be a gas mask filter? It was developed at the beginning of World War I to replace cotton, which was then in short supply as a surgical dressing.
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| Number | Title | Issue Date |
| 8112466 | Field programmable gate array An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a hig... | 02/07/2012 |
| 8082283 | Arrangement of 3-input LUT'S to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 12/20/2011 |
| 7991812 | Programmable logic devices with function-specific blocks A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the u... | 08/02/2011 |
| 7899857 | CPU datapipe architecture with crosspoint switch Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multipli... | 03/01/2011 |
| 7814136 | Programmable logic systems and methods employing configurable floating point units A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configurat... | 10/12/2010 |
| 7783693 | Reconfigurable circuit A reconfigurable circuit is provided, which includes a first arithmetic unit that performs addition or subtraction of a first input data and a second input data and outputs output data, and a first selector that selects an output data of the first arithmetic unit or... | 08/24/2010 |
| 7765249 | Use of hybrid interconnect/logic circuits for multiplication Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select int... | 07/27/2010 |
| 7765250 | Data processor with internal memory structure for processing stream data There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a c... | 07/27/2010 |
| 7587438 | DSP processor architecture with write datapath word conditioning and analysis An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving wor... | 09/08/2009 |
| 7580963 | Semiconductor device having an arithmetic unit of a reconfigurable circuit configuration in accordance with stored configuration data and a memory storing fixed value data to be supplied to the arithmetic unit, requiring no data area for storing fixed value data to be set in a configuration memory A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied ... | 08/25/2009 |
| 7571198 | Dynamically reconfigurable processor and processor control program for controlling the same A dynamically reconfigurable processor is provided having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area. A first wire permits a first arrangement of circuit blocks and a second wire provided for changing the... | 08/04/2009 |
| 7565387 | Systems and methods for configuring a programmable logic device to perform a computation using carry chains The disclosed invention is a technology for configuring a programmable logic device to perform a computation using carry chains. A computation having multiple input values can be decomposed into sub-computations that have a few input values each. The sub-computation... | 07/21/2009 |
| 7392332 | Bit rate adaptation in a data processing flow A dedicated processing module includes an input for data to be processed and an output for processed data. A block input and a block output are also included. A processing component for the module performs a digital processing operation on the data present at the da... | 06/24/2008 |
| 7346761 | Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical ope... | 03/18/2008 |
| 7269616 | Transitive processing unit for performing complex operations The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of a... | 09/11/2007 |
| 7254157 | Method and apparatus for generating a phase locked spread spectrum clock signal A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequenc... | 08/07/2007 |
| 7253658 | Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure A programmable integrated circuit (IC) provides high routing flexibility without the use of an output multiplexer structure. According to one embodiment, an IC includes programmable tiles arrayed in rows and columns. Output multiplexer structures are not included in... | 08/07/2007 |
| 7251672 | Reconfigurable logic device A reconfigurable logic device according to the invention comprises a lookup table (LUT) (11.1) with an input (in 1) for receiving an input signal and an output (out) for providing a binary output signal. The reconfigurable logic device is characterized... | 07/31/2007 |
| 7196541 | Electronic circuit with array of programmable logic cells An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an inpu... | 03/27/2007 |
| 7191312 | Configurable interconnection of multiple different type functional units array including delay type for different instruction processing An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input ... | 03/13/2007 |
| 7183642 | Electronic package with thermally-enhanced lid Removing heat generated by an operating IC chip from both the chip and the electronics package containing the chip is essential for proper system operation and to increase the life of the electronics package. Using an air permeable lid with the electronic package in... | 02/27/2007 |
| 7185035 | Arithmetic structures for programmable logic devices According to some embodiments, arithmetic structures in logic elements result from combining inverters and pass gates (or other multiplexing hardware) with LUT hardware. According to other embodiments, arithmetic structures in logic elements result from combining de... | 02/27/2007 |
| 7164288 | Electronic circuit with array of programmable logic cells An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an inpu... | 01/16/2007 |
| 7157934 | Programmable asynchronous pipeline arrays High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the desi... | 01/02/2007 |
| 7142669 | Circuit for generating hash values A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file (12) ... | 11/28/2006 |
| 7140003 | Method and system for specifying sets of instructions for selection by an instruction generator A method for specifying a set of instructions selectable for generation by an instruction generator is disclosed. A class name representative of a class of instructions is identified and concatenated with a unique identifier label, thereby defining a unique singleto... | 11/21/2006 |
| 7133820 | Method and apparatus for debugging programs in a distributed environment A method and apparatus for debugging programs in a distributed environment, such as a set of heterogeneous hardware processors (integrated circuits or In-Circuit Emulators), and/or software-based simulators. In one embodiment, the method comprises identifying a plur... | 11/07/2006 |
| 7112994 | Three dimensional integrated circuits A mask configurable semiconductor device, comprising: a first module layer having a plurality of circuit blocks including at least one programmable logic block; and a second module layer deposited substantially above the first module layer, including a read only mem... | 09/26/2006 |
| 7092980 | Programming architecture for a programmable analog system A programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled t... | 08/15/2006 |
| 7088860 | Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement info... | 08/08/2006 |
| 7062520 | Multi-scale programmable array A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called ... | 06/13/2006 |
| 7062635 | Processor system and method providing data to selected sub-units in a processor functional unit A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 54... | 06/13/2006 |
| 7053653 | Inter-tile buffer system for a field programmable gate array An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each tile comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the f... | 05/30/2006 |
| 7051059 | Oversampling FIR filter, method for controlling the same, semiconductor integrated circuit having the same, and communication system for transmitting data filtered by the same When changing the number of oversamples is performed, tap factors selected by selectors, which respectively correspond to holding parts in a shift register, are changed back to a predetermined number of tap factors used before the changing of the number of oversampl... | 05/23/2006 |
| 7046723 | Digital filter and method for performing a multiplication based on a look-up table A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are perfor... | 05/16/2006 |
| 7043511 | Performing conditional operations in a programmable logic device A vector-domain engine configured to perform conditional operations on an operand vector in a programmable logic device is disclosed. The vector-domain engine may receive an instruction from and transmit an output vector to a programmable-logic-device domain. The ou... | 05/09/2006 |
| 7035886 | Re-configurable combinational logic device A re-configurable combinational logic device. The device comprises combinational logic that inputs a number of signals and a memory array for storing data to define Boolean expressions for a number of states. The states have Boolean expressions of selected signals o... | 04/25/2006 |
| 7024653 | Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD) According to one embodiment, an integrated circuit (100) includes a programmable portion (102) and a communication portion (104). A programmable portion (102) may include logic circuits that are configurable by a user. A communication por... | 04/04/2006 |
| 7020673 | Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system An arithmetic device able to optimize the logic level, able to prevent an increase in the component data, able to prevent the area efficiency as an integrated operation efficiency, and circuit, achieving an improvement in the achieving a reduction power consumption,... | 03/28/2006 |
| 7003545 | High performance carry chain with reduced macrocell logic and fast carry lookahead A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B... | 02/21/2006 |
