Bizarre Patents
Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 8010586 | Apparatus and method of generating DBI signal in semiconductor integrated circuit An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and ... | 08/30/2011 |
| 8005880 | Half width counting leading zero circuit A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most... | 08/23/2011 |
| 7958173 | Population count approximation circuit and method thereof A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which rece... | 06/07/2011 |
| 7603398 | Data converter and a delay threshold comparator For one disclosed embodiment, a converter converts 2N-bit data into an N-bit value indicating a number of bits in the data that have a predetermined logical value. The converter includes N comparators, each determining whether the number of bits in the da... | 10/13/2009 |
| 7363423 | Multiple match detection circuit Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR (xi AND xj), where xi=x1, x | 04/22/2008 |
| 7349934 | Processor system and method with combined data left and right shift operation An integrated circuit device (100) includes circuitry for providing a first shift argument (L[4:0]) indicating shift positions in a first direction and circuitry for providing a second shift argument (R[4:0]) indicating shift positions in a second direction. ... | 03/25/2008 |
| 7275076 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 09/25/2007 |
| 7271757 | Encoder circuit and A/D conversion circuit An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer ... | 09/18/2007 |
| 7237100 | Transaction redirection mechanism for handling late specification changes and design errors Redefined hardware structured transactions and the associated responses in a data processing device are made user programmable. Three registers, a identifier register, a mask register and a response register, are used to redirect transactions or other operations wit... | 06/26/2007 |
| 7218138 | Efficient implementations of the threshold-2 function A circuit and a method for operating the circuit are disclosed. A first step of the method generally comprises generating a plurality of first intermediate signals in two parallel first operations each responsive to a respective half of a plurality of input signals.... | 05/15/2007 |
| 7215259 | Data compression with selective encoding of short matches A method and apparatus for encoding a sequence of input data into a sequence of coded data, where the coded data is represented as literal data, as single-character references to recent input data, and as a references to one or more past input data. The references m... | 05/08/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7142669 | Circuit for generating hash values A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file (12) ... | 11/28/2006 |
| 7139788 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 11/21/2006 |
| 7136888 | Parallel counter and a logic circuit for performing multiplication A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of co... | 11/14/2006 |
| 7116663 | Multi-field classification using enhanced masked matching Methods and apparatus for finding a match between a target bit pattern and multiple filter bit patterns. A filter array is created from the filter bit patterns and at least one intermediate array is generated from the filter array. Specific columns of the intermedia... | 10/03/2006 |
| 7111033 | Carry save adders A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arrang... | 09/19/2006 |
| 7062633 | Conditional vector arithmetic method and conditional vector arithmetic unit It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision... | 06/13/2006 |
| 7043520 | High-speed/low power finite impulse response filter A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response f... | 05/09/2006 |
| 7042246 | Logic circuits for performing threshold functions Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic... | 05/09/2006 |
| 7020865 | Process for designing comparators and adders of small depth Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f′N=x1 AND (x2 OR (x3 AND (x4 ... | 03/28/2006 |
| 6963887 | Method and device for performing data pattern matching A method and system for identifying a bit pattern in a data stream including a plurality of bits each having a first or second state, the method includes identifying a number of mismatching bits, within a subset of the plurality of bits, having the first state and c... | 11/08/2005 |
| 6958925 | Staggered compare architecture for content addressable memory (CAM) device A content addressable memory (CAM) device (300) can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (302-0) and another being... | 10/25/2005 |
| 6938061 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary... | 08/30/2005 |
| 6909767 | Logic circuit Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the fir... | 06/21/2005 |
| 6889235 | Method and apparatus for quantifying the number of identical consecutive digits within a string One embodiment of the present invention provides a system for quantifying a number of identical consecutive digits starting from a fixed position within a string of n digits. The system operates by converting the string of n digits into a thermometer code, wherein t... | 05/03/2005 |
| 6883011 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binar... | 04/19/2005 |
| 6795839 | Method and device for computing the number of bits set to one in an arbitrary length word A method and a bit counting device (100) count bits set to one in a data word of arbitrary size. The bit counting device (100) includes a first data register (110) for storing a data word, an offset register (112) for storing an offset va... | 09/21/2004 |
| 6781528 | Vector handling capable processor and run length encoding Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a pluralit... | 08/24/2004 |
| 6754685 | Dynamic popcount/shift circuit A method for integrating population count operations with bit shift operations has been developed. The method can be used for incrementing a pointer by a population count of a sparse vector. The method further provides for balancing the input loads at the inputs of ... | 06/22/2004 |
| 6665691 | Circuit for detecting numbers equal to a power of two on a data bus There is disclosed a circuit for determining if an N-bit number is equal to a power of two. The circuit comprises: 1) a first stage of detection gates, each of the first stage detection gates capable of receiving a first data bit and a second data bit fro... | 12/16/2003 |
| 6636881 | Binary data counter, area information extractor and huffman converter In order to provide an inexpensive binary data counting device of which the processing is done at high speed and which can be implemented with a small circuit scale, a shifter array 10 is provided for outputting binary data of N bits, which comprises N×(... | 10/21/2003 |
| 6516330 | Counting set bits in data words Counting the number of set bits in an n-bit data word in a data processing system. The process involves generating at least p1 intermediate n-bit words, where 1 | 02/04/2003 |
| 6513053 | Data processing circuit and method for determining the first and subsequent occurences of a predetermined value in a sequence of data bits An apparatus and method is provided for determining locations of a predetermined value in a sequence of data bits. Each location is determined independently of the others thereby allowing them to be found more quickly. This has particular application to b... | 01/28/2003 |
| 6434488 | Alignment free methodology for rapid determination of differences between a test data set and known data sets A method for generating data characterizing an item described by an ordered string of characters, comprises the steps of: (i) for a set of separation metrics each representing a unique number of positions of separation between arbitrary characters in a ch... | 08/13/2002 |
| 6430251 | 4-Bit population count circuit An electronic device that counts the number of set bits in an input vector and asserts an output vector representative of the number of set bits. The electronic device uses a combination of dynamic logic components and static logic components to minimize ... | 08/06/2002 |
| 6272511 | Weightless binary N-tuple thresholding hierarchies A novel architecture is described for applying a sum and threshold function to a weightless input string and a weightless threshold string. The sum and threshold function is carried out by distributing the input bits in random manner (12) between a number of s... | 08/07/2001 |
| 5995029 | Parallel bit counter using bit sorters A parallel bit counter for counting the number of bits having a particular level in parallel input data. The counter includes a 2-bit sorter adapted to sort "high" and "low" bit fields of parallel input data in accordance with a bit sort method, and a cas... | 11/30/1999 |
| 5978827 | Arithmetic processing In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high... | 11/02/1999 |
| 5948048 | Systems, methods and program products for representing a binary word as two binary words having fewer binary ones First and second binary words representing a third binary word having a predetermined number of bits are determined in a data processing system by storing a first word the same as the third binary word and storing a second word having the predetermined nu... | 09/07/1999 |
