Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5086405 | Floating point adder circuit using neural network A floating point adder circuit using neural network concepts and having high speed operation is obtained by a controlling circuit using a comparator and an operating circuit using an adder and a subtractor.... | 02/04/1992 |
| 5075882 | Normalizing circuit of floating-point arithmetic circuit for two input data A post-normalizing unit for use in a floating-point arithmetic circuit having a pre-normalizing unit for carrying out a pre-normalization operation on first and second exponent parts and first and second fraction parts to produce a maximum exponent part a... | 12/24/1991 |
| 5040138 | Circuit for simultaneous arithmetic calculation and normalization estimation An arithemtic circuit (10) which comprises an adder/rounder circuit (20) and a normalization estimation circuit (24) coupled in parallel to operand register (14, 19). A signed digit subtracter (25) subtracts the operands and inputs a signed digit differen... | 08/13/1991 |
| 5038310 | Amplitude compressing and/or expanding circuit employing enhanced normalization In a circuit for expanding and/or compressing an amplitude of an input signal; a control signal is generated in response to the input signal and supplied to a multiplier circuit for multiplying the input signal by the control signal, a first subtracter su... | 08/06/1991 |
| 5027308 | Circuit for adding/subtracting two floating point operands In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa no... | 06/25/1991 |
| 5010508 | Prenormalization for a floating-point adder In a floating-point subtraction of two numbers where a normalized result is needed, a prenormalization circuit predicts the number of leading zeroes which will appear in the resultant mantissa, due to the close value of the two source operands. The prenor... | 04/23/1991 |
| 4994996 | Pipelined floating point adder for digital computer A system for subtracting two floating-point binary numbers in a pipelined floating-point adder/subtractor by aligning the two fractions for sustraction; arbitrarily designating the fraction of one of the two floating-point numbers as the subtrahend, and p... | 02/19/1991 |
| 4991130 | Normalization control system for floating point arithmetic operation A microprogram controlled microprocessor capable of normalizing a given data in a floating point representation includes a memory storing a microprogram, an address register for holding a microprogram start address, an operand register for holding a sourc... | 02/05/1991 |
| 4977535 | Method of computation of normalized numbers Floating point numbers are processed by an apparatus, where an increment step may be necessary on a number but where that number may or may not have to be normalized, depending on the computation. The invention is particularly useful in rounding after mul... | 12/11/1990 |
| 4947358 | Normalizer for determining the positions of bits that are set in a mask A normalizer that identifies the bits that are set in input data and generates output signals representing the positions of the set bits in the input data. The normalizer has a device arranged to receive an n-bit signal. Each of the bits of the n-bit sign... | 08/07/1990 |
| 4941120 | Floating point normalization and rounding prediction circuit Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enab... | 07/10/1990 |
| 4926370 | Method and apparatus for processing postnormalization and rounding in parallel A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, an... | 05/15/1990 |
| 4926369 | Leading 0/1 anticipator (LZA) A method and system for performing a leading 0/1 anticipation (LZA) in parallel with the floating-point addition of two operands (A and B) in a computer to significantly reduce the Addition-Normalization time. A combinational network is used to process ap... | 05/15/1990 |
| 4922446 | Apparatus and method for floating point normalization prediction The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point ad... | 05/01/1990 |
| 4905178 | Fast shifter method and structure Normalization and scaling operations are performed by the use of the fast shifter of a micrprocessor operating in response to the system clock, rather than in response to microinstructions. By local control of the fast shifter, multiple shift steps essent... | 02/27/1990 |
| 4864527 | Apparatus and method for using a single carry chain for leading one detection and for "sticky" bit calculation In a floating point addition or subtraction procedure two shift operations of the operand fraction may be required. The first shift operation, based on the difference between the operand exponent arguments, involves aligning one of the operand arguments s... | 09/05/1989 |
| 4794557 | Floating-point normalizing circuit A floating-point normalizing circuit is adapted to receive two multi-bit numbers so as to generate a signal indicative of a shift amount for floating-point normalization. The normalizing comprises a plurality of unitary circuits each including a pair of b... | 12/27/1988 |
| 4789956 | Maximum negative number detector Prior to normalizing floating point number, a maximum negative number detector is employed. In order to determine whether a number is a maximum negative number, the inventive scheme examines the left-most (most significant) bit of the bit sequence to be s... | 12/06/1988 |
| 4785421 | Normalizing circuit A normalizing circuit is disclosed which can make bit shift operation for a bit string. The normalizing circuit has a leading "one" detector, an encoder and a bit shifter. The leading "one" detector detects a bit position of a leading "one" among a bit st... | 11/15/1988 |
| 4782457 | Barrel shifter using bit reversers and having automatic normalization A barrel shifter for a floating point processing unit can be optimized by having an automatic normalization feature. A multi-stage shifting unit is employed with external circuitry to verify that only leading zeros would be shifted out before activating a... | 11/01/1988 |
| 4779220 | Floating-point data rounding and normalizing circuit A floating-point data rounding and normalizing circuit comprises a shift controller receiving a fraction portion of an input floating-point data for generating a shift control signal indicative of a shift amount required for normalization. A barrel shifte... | 10/18/1988 |
| 4773033 | Binary data identification circuit A binary data identification circuit including first and second potential terminals set to first and second logical potential levels, a series circuit including first to (n-1)th transfer gates whose conduction states are controlled responsive to 1st to (n... | 09/20/1988 |
| 4758974 | Most significant digit location After performing a floating point addition, it is desired to normalize the sum; that is, shift the most significant digit of the mantissa into the left-most digit location, and adjust the exponent accordingly. Prior art techniques required performing the ... | 07/19/1988 |
| 4586154 | Data word normalization A data word (bits ID.0.-ID15) is supplied to the address inputs of a memory arrangement U1, U2, U3 whose outputs S0-S3 supply to a parallel shifter SN a control word specifying the number of shifts required. As described, two read-only memories receive re... | 04/29/1986 |
| 4553220 | Matrix multiplier with normalized output A matrix multiplier having application to a real time computer-generated imagery or graphics system, wherein the output of the multiplier is normalized to increase both the accuracy and speed by which a three dimensional object can be displayed on a video... | 11/12/1985 |
| 4528640 | Method and a means for checking normalizing operations in a computer device A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is use... | 07/09/1985 |
