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| Number | Title | Issue Date |
| 8046395 | Normalization processing apparatus A normalization processing apparatus according to an embodiment of the present invention can calculate all of normalization processing output values, that is, the output value of the size of a region, the output value of the lowest value in the region, the output va... | 10/25/2011 |
| 7698353 | Floating point normalization and denormalization A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is par... | 04/13/2010 |
| 7668892 | Data processing apparatus and method for normalizing a data value A data processing apparatus and method are provided for normalizing a data value to produce a result value. The data processing apparatus includes prediction logic for generating a shift indication based on a prediction of the number of bit positions by which the da... | 02/23/2010 |
| 7430656 | System and method of converting data formats and communicating between execution units A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to t... | 09/30/2008 |
| 7337202 | Shift-and-negate unit within a fused multiply-adder circuit A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and... | 02/26/2008 |
| 7321914 | Fast method for calculating powers of two as a floating point data type A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment supporting a union declaration functionality and a left shift function... | 01/22/2008 |
| 7320013 | Method and apparatus for aligning operands for a processor A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second opera... | 01/15/2008 |
| 7248700 | Device and method for calculating a result of a modular exponentiation In a device for calculating a result of a modular exponentiation, the Chinese Residue Theorem (CRT) is used, wherein two auxiliary exponentiations are calculated using two auxiliary exponents and two sub-moduli. In order to improve the safety of the RSA CRT calculat... | 07/24/2007 |
| 7212596 | Data detection circuit and method A data detection circuit and method detect a first bit that is the least significant among bits having a value 1 in N-bit input binary data and a second bit that is the second least significant among bits having the value 1 in the N-bit input data. The data detectio... | 05/01/2007 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 03/27/2007 |
| 7099910 | Partitioned shifter for single instruction stream multiple data stream (SIMD) operations A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normaliz... | 08/29/2006 |
| 7096241 | Exponent encoder circuit and mask circuit In order to provide an exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code bits, there is provided a first logic circuit for inverting data portions other than code bits and shifting the code bit... | 08/22/2006 |
| 7086004 | Generalized mechanism for unicode metadata A extendable method for including display rendering metadata within Unicode character streams. Metadata is distinct from character data, even though it is embedded in the Unicode character stream using tag mechanism. The method allows for an unlimited number of tag ... | 08/01/2006 |
| 7080111 | Floating point multiply accumulator A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accu... | 07/18/2006 |
| 7062525 | Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporati... | 06/13/2006 |
| 7062635 | Processor system and method providing data to selected sub-units in a processor functional unit A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 54... | 06/13/2006 |
| 7062657 | Methods and apparatus for hardware normalization and denormalization Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normali... | 06/13/2006 |
| 7043516 | Reduction of add-pipe logic by operand offset shift The shifters (30, 32) that a floating-point processor (10)'s addition pipeline (14) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction... | 05/09/2006 |
| 6988115 | Method and apparatus to correct leading one prediction A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a o... | 01/17/2006 |
| 6981012 | Method and circuit for normalization of floating point significants in a SIMD array MPP The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for p... | 12/27/2005 |
| 6976153 | Floating point unit with try-again reservation station and method of operation A floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages for executing floating point operations in a series of sequential steps; and 2) a try-again reservation station for storing a plurality of instructions to be loaded... | 12/13/2005 |
| 6957238 | Method and system for deterministic pseudo-random valid entry resolution The present invention provides a method and system to select a valid entry in a deterministic pseudo-random approach. The method may randomly select one of numerous valid entries in order to ensure that no specific entry or set of entries is consistently ignored. Mo... | 10/18/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6938060 | Apparatus and method for graphically displaying a vector simultaneously along with the numerical values of its vector components A handheld computing device (40) comprises a software application adapted to provide instructions to graphically display a vector on a display screen (48) simultaneously along with the numerical values for components of the vector. The software applica... | 08/30/2005 |
| 6922159 | Apparatus and method for decoding Coding section 205 recodes decoded data stored in decoded data storage section 204, data conversion section 206 converts data “0” and “1” output from coding section 205 to “1” and “−1” respectively, sum-of-product calcul... | 07/26/2005 |
| 6904518 | Finding a significant bit in a computer data word The most or least significant bit of a datum can bet determined using parallel operations. This may result in faster location of the most or least significant bit without necessarily introducing more overhead in some embodiments. ... | 06/07/2005 |
| 6901503 | Data processing circuits and interfaces An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processo... | 05/31/2005 |
| 6779008 | Method and apparatus for binary leading zero counting with constant-biased result A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are generated. The subvector leading-zero counts are biased by a constant... | 08/17/2004 |
| 6765515 | Arithmetic coding/decoding apparatus of MQ-Coder system and renormalization method In a renormalization processing device of MQ-CODER, the value of an augend register A is calculated by a shift quantity calculating unit without performing loop processing, and the number of left shifts SHIFT_A of A up to the end of renormalization processing is cal... | 07/20/2004 |
| 6760738 | Exponent unit of data processing system An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB) of the operand. The exponent unit can obtain an exponent value of an... | 07/06/2004 |
| 6754688 | Method and apparatus to calculate the difference of two numbers An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the first detection bits indicate a difference of zero. A second module gener... | 06/22/2004 |
| 6675376 | System and method for fusing instructions A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fus... | 01/06/2004 |
| 6671796 | Converting an arbitrary fixed point value to a floating point value A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floa... | 12/30/2003 |
| 6622118 | System and method for comparing signals A method and system that include a first measurement signal and a second measurement signal that can be input to first and second filters. The filters can be subject to a first constraint to minimize the energy difference between the first and second meas... | 09/16/2003 |
| 6571264 | Floating-point arithmetic device A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the remaining significand by the calculated exponent difference,... | 05/27/2003 |
| 6499044 | Leading zero/one anticipator for floating point An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level... | 12/24/2002 |
| 6360238 | Leading zero/one anticipator having an integrated sign selector A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floa... | 03/19/2002 |
| 6301594 | Method and apparatus for high-speed exponent adjustment and exception generation for normalization of floating-point numbers A method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1) generating a shift count indicating the number of bit positions, i... | 10/09/2001 |
| 6289366 | Speedy shift apparatus for use in arithmetic unit An shift circuit is used in an arithmetic unit, for shifting m-bit input data to left or in right, m being a positive integer. The shift circuit includes a latch for temporarily storing the m-bit input data and additional 2n-bit, wherein n is a positive i... | 09/11/2001 |
| 6219682 | Vector normalizing apparatus A vector normalizing apparatus in which information concerning the norm of the original vector is not lost by normalization, and which needs no device that divides vector components by norm. The apparatus includes a vector input device (1) for entering a ... | 04/17/2001 |
