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| Number | Title | Issue Date |
| 8131788 | Determining sum of absolute differences in parallel Determining a sum of absolute differences using a circuit is described. Pairs of inputs, including a respective current value and a respective previous value, are obtained. The previous value is subtracted from the current value for each of the pairs of inputs to pr... | 03/06/2012 |
| 8051116 | Apparatus and method for generating packed sum of absolute differences A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed difference... | 11/01/2011 |
| 7480685 | Apparatus and method for generating packed sum of absolute differences A microprocessor for generating a packed sum of absolute differences is disclosed. The microprocessor includes an instruction translator, for translating a Multimedia Extensions (MMX) Packed Sum of Absolute Differences Byte to Word (PSADBW) macroinstruction into at ... | 01/20/2009 |
| 7430573 | Processor In a processor, an ALU or a decode portion comprises a sign reversal portion 101 for reversing the sign of a first input value, a sign determination portion 102 for determining the sign of a second input value, and an output selection portion 103 | 09/30/2008 |
| 7424501 | Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations Nonlinear filtering and deblocking applications utilizing SIMD (single instruction multiple data) sign and absolute value operations are disclosed. The method of one embodiment includes receiving first data for a first block and second data for a second block. The f... | 09/09/2008 |
| 7386580 | Data processing apparatus and method for computing an absolute difference between first and second data elements A data processor computes an absolute difference between portions of first and second data elements. At least a part of the first and second data elements are compared to determine which data element is larger. A first comparison result value is produced if the firs... | 06/10/2008 |
| 7376686 | Apparatus and method for generating packed sum of absolute differences An apparatus for performing an MultiMedia extension (MMX) Packed Sum of Absolute Differences (PSADBW) instruction is disclosed. The apparatus includes carry-generating subtraction logic that generates packed differences of the subtrahend from the minuend and associa... | 05/20/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7283526 | Method and system for providing a symmetric key for more efficient session identification A method and system for identifying sessions in a computer network is disclosed. The session is between a first computer system and a second computer system. The session consists of an exchange of a plurality of packets between the computer systems. Each of the pack... | 10/16/2007 |
| 7227994 | Method and apparatus for imbedded pattern recognition using dual alternating pointers A method and apparatus for finding a reference pattern (RP) with K elements imbedded in an input pattern IP with repeating substrings uses dual pointers to point to elements in the RP to compare with input elements sequentially clocked from the IP. The dual pointers... | 06/05/2007 |
| 7213131 | Programmable processor and method for partitioned group element selection operation A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data ... | 05/01/2007 |
| 7200629 | Apparatus and method for Fast Hadamard Transforms A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator comprises a series of stages. Each stage includes a shift register for serially receiving samples of the s... | 04/03/2007 |
| 7191199 | Method and device for computing an absolute difference Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders (24). The second value is subtracted from the first value using the pr... | 03/13/2007 |
| 7143335 | Add-compare-select arithmetic unit for Viterbi decoder An add-compare-select (ACS) arithmetic unit for a Viterbi decoder is provided. The ACS arithmetic unit includes two 2's complement adders for performing an operation on a state metric related to a bit value 0 and a state metric related to a bit value 1, respectively... | 11/28/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7110442 | Method and apparatus for fast acquisition and low SNR tracking in satellite positioning system receivers A satellite positioning system (SATPS) receiver has a mix of standard and enhanced digital channel processors. The standard digital channel processors perform continuous tracking. During a low SNR and/or fast acquisition mode, the enhanced digital channel processor ... | 09/19/2006 |
| 7054895 | System and method for parallel computing multiple packed-sum absolute differences (PSAD) in response to a single instruction A system and method are presented in which multiple packed-sum absolute differences (PSAD) are computed in response to a single instruction. One embodiment of the system comprises a first register configured to store a first operand having data elements, and a secon... | 05/30/2006 |
| 6999981 | Circuit for computing the absolute value of complex numbers An apparatus (100) for computing the absolute value of a complex number includes separate squaring units (110, 115) for the real and imaginary parts. A square root unit (130) extracts the square root of the sum (120) of these squares, whi... | 02/14/2006 |
| 6959316 | Dynamically configurable processor A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having inputs that are switchably or programmably coupled, in a first mode of ope... | 10/25/2005 |
| 6943810 | Layered article data verification A method, system and program product to verify a data preparation employed on a plurality of design layers that make up an article. An instruction algorithm representative of the data preparation is restated in terms of fundamental algorithms having corresponding gr... | 09/13/2005 |
| 6920473 | Method and apparatus for modular multiplying and calculating unit for modular multiplying A multiplicand is multiplied by a multiplier using a modulus. The multiplicand, the multiplier and the modulus are polynomials of variable. A multiplication look-ahead method to obtain a multiplication shift value is carried out. An intermediate result polynomial is... | 07/19/2005 |
| 6907443 | Magnitude comparator A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be c... | 06/14/2005 |
| 6907441 | Square root extractor A square root extractor includes only multipliers, summers, delay elements, and a scaler so that the square root of a signal may be produced without complex computations. ... | 06/14/2005 |
| 6888879 | Method and apparatus for fast acquisition and low SNR tracking in satellite positioning system receivers A satellite positioning system (SATPS) receiver has a mix of standard and enhanced digital channel processors. The standard digital channel processors perform continuous tracking. During a low SNR and/or fast acquisition mode, the enhanced digital channel processor ... | 05/03/2005 |
| 6820102 | DSP unit for multi-level global accumulation In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) ... | 11/16/2004 |
| 6738973 | Access-history indicating method and apparatus, resources providing method and apparatus, and program providing medium used therewith An access-history indicating method sequentially records a history of access by a user to a resource object such as a file or a WWW page. In the method, an access history icon that visually represents access-history information is generated and is displayed in the v... | 05/18/2004 |
| 6691145 | Computing circuit, computing apparatus, and semiconductor computing circuit A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suita... | 02/10/2004 |
| 6622118 | System and method for comparing signals A method and system that include a first measurement signal and a second measurement signal that can be input to first and second filters. The filters can be subject to a first constraint to minimize the energy difference between the first and second meas... | 09/16/2003 |
| 6601077 | DSP unit for multi-level global accumulation In one embodiment, a digital signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic un... | 07/29/2003 |
| 6594396 | Adaptive difference computing element and motion estimation apparatus dynamically adapting to input data An adaptive difference computing element which consumes less power without any decrease in calculation accuracy includes: a first circuit receiving first and second data with the same bit lengths and each having bits at one and the other ends, determining... | 07/15/2003 |
| 6578060 | Floating-point calculation apparatus A value of difference between exponent values and an inverted value thereof obtained by an inverting circuit are calculated using one subtractor and one of the value of the difference and the inverted value of the difference is selected in accordance with... | 06/10/2003 |
| 6401108 | Floating point compare apparatus and methods therefor Floating-point compare apparatus and methods are implemented. An adder generates a difference in moduli of first and second input operands. A sign bit of the second input operand provides a carry-in bit to an adder. In a first embodiment, the first and se... | 06/04/2002 |
| 6282556 | High performance pipelined data path for a media processor A pipelined data path architecture for use, in one embodiment, in a multimedia processor. The data path architecture requires a maximum of two execution pipestages to perform all instructions including wide data format multiply instructions and specially ... | 08/28/2001 |
| 6073150 | Apparatus for directing a parallel processing computing device to form an absolute value of a signed value In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit m... | 06/06/2000 |
| 6036350 | Method of sorting signed numbers and solving absolute differences using packed instructions A technique for sorting packed signed numbers of two operands into maxima and minima operands and solving absolute differences for each pair of corresponding values of maxima and minima. After packing two source operands with a plurality of data elements ... | 03/14/2000 |
| 5983250 | Arithmetic circuit for obtaining absolute-valued distance There is disclosed a compact arithmetic circuit for obtaining an absolute-valued distance (AVD) between two digital data. An inverter 11 generates the data * ଲ which is derived from the data ଲ as the 1's complement thereof. An ALU 12 adds the ... | 11/09/1999 |
| 5957996 | Digital data comparator and microprocessor The present invention provides a digital data comparator having a first selective data inverting circuit inverting a first input data when the sign of the first input data is negative, or outputting the first input data when the sign is positive, a first ... | 09/28/1999 |
| 5954786 | Method for directing a parallel processing computing device to form an absolute valve of a signed valve In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute value comprises the steps of: performing an arithmetic shift right of N-1 bit to form a bit m... | 09/21/1999 |
| 5944771 | Arithmetic operation system for binary addition/subtraction In an arithmetic operation circuit, a coincidence detector receives the sign bits of binary data so as to output a truth coincidence detection signal when the two sign bits coincide with each other, and to output a false coincidence detection signal when ... | 08/31/1999 |
| 5917732 | Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an ... | 06/29/1999 |
