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| Number | Title | Issue Date |
| 8095583 | Chaotic and fractal field line calculations using decomposition and self winding Faster methods for topological categorization and field line calculations are developed by using decomposition regions together with the self-winding techniques first developed in a prior patent application. A point iteration technique provides direct calculation of... | 01/10/2012 |
| 8078657 | Multi-source dual-port linked list purger Disclosed is a circuit for simultaneously searching two ends of a vector. The circuit comprises at least one input for receiving a vector of head pointers. A first input of a memory latch receives the vector of head pointers. An input of a first priority decoder rec... | 12/13/2011 |
| 8078656 | Data decompression with extra precision Methods and systems for decompressing data are described. The relative magnitudes of a first value and a second value are compared. The first value and the second value represent respective endpoints of a range of values. The first value and the second value each ha... | 12/13/2011 |
| 8060544 | Representation of data transformation processes for parallelization One or more operations are defined to be used against a repository of one or more items. One or more associations between each of the one or more items are also defined. A classification is associated with the one or more operations for an execution environment with... | 11/15/2011 |
| 8055694 | Modular investment position calculation A system and method for effecting modular investment position calculation is disclosed. The system and method comprise a data architecture having multiple stored calculation components. The calculation components include base calculation components and variant calcu... | 11/08/2011 |
| 8037114 | Method for creating a representation of a calculation result linearly dependent upon a square of a value In the transition into the logarithmic range, not the entire bit width of the result linearly dependent upon the square of the value must be considered. Rather, it is possible to scale the result of a value with x bits such that a representation with less than x bit... | 10/11/2011 |
| 8010585 | Checking the integrity of programs or the sequencing of a state machine A method and a circuit for protecting the execution of a calculation by an electronic circuit, conditioning a result of the calculation to states of bits indicative of executions of steps of access in read mode and/or in write mode to storage elements. ... | 08/30/2011 |
| 8001167 | Automatic BNE seed calculator An automatic background noise estimator (BNE) seed calculator for determining a starting point for a BNE circuit which tracks the noise floor received by a receiver. The BNE seed calculator may sample a plurality of data points from the receiver and calculate the ma... | 08/16/2011 |
| 7979480 | Discrete signal processing device and processing method A signal processing device and a signal processing method are provided which can reproduce a smooth signal in the reproduction of a discrete signal having a non-uniform sample point interval. The device includes a coefficient calculation unit 4 that inputs a ... | 07/12/2011 |
| 7962537 | Determining a table output of a table representing a hierarchical tree for an integer valued function Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and... | 06/14/2011 |
| 7945606 | Method and apparatus for evaluating a time varying signal A method for evaluating a received signal varying over an interval includes: (a) obtaining a data sample and a sample time; (b) determining whether the sample exceeds a previous exceeded extremum of the signal; (c) if the sample does not exceed an exceeded extremum,... | 05/17/2011 |
| 7937425 | Scalable 2×2 rotation processor for singular value decomposition A two-plane rotation (TPR) approach to Gaussian elimination (Jacobi) is used for computational efficiency in determining rotation parameters. A rotation processor is constructed using the TPR approach to perform singular value decomposition (SVD) on two by two matri... | 05/03/2011 |
| 7937426 | Interval generation for numeric data Embodiments of the present invention relate to the generation of intervals from a selection of numeric data. An interval is a set of numeric data that is organized between two numeric values that may include one or both of those numeric values. In an embodiment, a d... | 05/03/2011 |
| 7933940 | Cyclic segmented prefix circuits for mesh networks Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh are arranged in row-major order. Values are accumulated toward the cent... | 04/26/2011 |
| 7930330 | Scaled exponential smoothing A method and system for scaled exponential smoothing are provided. Multiple exponentially smoothed values are maintained for items and events occur on one or more of the items. The method maintains a gradually inflated representation of the smoothed values of items,... | 04/19/2011 |
| 7877428 | Processor system including processor and coprocessor A processor includes a first register, a control section and an arithmetical section. The processor has a first operation mode which allows the first area of a first register to be accessed and a second operation mode which allows a second area of the first register... | 01/25/2011 |
| 7836111 | Detecting change in data To detect a change in data produced by a system, predicted data values for plural time points are computed. Actual data values for the plural time points are received, and residual values are derived from differences between the predicted data values and actual data... | 11/16/2010 |
| 7836112 | Determining the equivalence of two sets of simultaneous linear algebraic equations A computer implemented method (200) is described for determining the equivalence of two sets of simultaneous linear algebraic equations. Each of said equations is of a form: ei1x1+ei2x | 11/16/2010 |
| 7809781 | Determining a time point corresponding to change in data values based on fitting with respect to plural aggregate value sets Aggregation of data values in a data set is computed to produce aggregate values. The aggregate values are partitioned into plural aggregate value sets. Fitting with respect to the plural aggregate value sets is performed. Based on the fitting, at least one time poi... | 10/05/2010 |
| 7801934 | Pointer generation method and apparatus for delay compensation in virtual concatenation applications Virtual concatenation circuitry is disclosed for implementation in a network element of a data communication network. The virtual concatenation circuitry in a preferred embodiment is operative: (i) to maintain, for each of the individual member streams of a virtual ... | 09/21/2010 |
| 7783691 | Sharing of a logic operator having a work register A circuit for calculating a discriminating function with successive iterations and with a work register on data divided into blocks, including: a single operator in wired logic for executing the function; a plurality of work registers sharing the operator; and an el... | 08/24/2010 |
| 7783690 | Electronic circuit for implementing a permutation operation A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizo... | 08/24/2010 |
| 7739319 | Method and apparatus for parallel table lookup using SIMD instructions Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table having a set of L data elements. A determination of whether the table fits into a single register is made. A d... | 06/15/2010 |
| 7725512 | Apparatus and method for performing multiple exclusive or operations using multiplication circuitry An apparatus and method for performing multiple exclusive OR (XOR) operations using standard binary multiplication circuitry to create multiple XOR expressions simultaneously. The method and apparatus include a multiplication circuit to generate a product result by ... | 05/25/2010 |
| 7693921 | Reducing computational complexity in determining the distance from each of a set of input points to each of a set of fixed points An aspect of the present invention takes advantage of the fact that the coordinates of fixed points do not change, and thus the energy (sum of squares of the coordinates defining the vector) of each fixed point is computed and stored. The energy of each variable inp... | 04/06/2010 |
| 7685212 | Fast full search motion estimation with SIMD merge instruction A method for a fast full search motion estimation with SIMD merge instruction. The method of one embodiment comprises loading a first line of K data elements for a current macroblock. A first set of L data elements and a second set of L data elements for pixels in a... | 03/23/2010 |
| 7676527 | Processor The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means i... | 03/09/2010 |
| 7676528 | Image data processing apparatus and image data processing method An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added da... | 03/09/2010 |
| 7676529 | System and method for efficient rectangular to polar signal conversion using cordic algorithm A system and method is provided for converting an input signal from a sequence of rectangular coordinate pairs to a sequence of polar coordinate pairs. The input signal includes a sequence of input vectors each including a pair of rectangular coordinates. A pluralit... | 03/09/2010 |
| 7668891 | Adjustable time accumulator A time accumulator is adjustable to provide sufficient calculation time regardless of the clock frequency. The time accumulator includes a first register storing a current time and a second register storing a time increment value corresponding to a multiplier multip... | 02/23/2010 |
| 7653673 | Efficient method for identifying few largest differences from a list of numbers A method is provided that finds the largest ‘k’ difference values in decreasing order from a list of ‘n’ arbitrary numbers. The method uses the property of sorted numbers to organize the list of all the differences in a way that reduces the size of the solut... | 01/26/2010 |
| 7627622 | System and method of curve fitting The invention relates to fitting a curve to a plurality of data points. A “seed curve” is determined from a first set of data points selected from the plurality of data points. From the remaining data points, data points are individually selected and a determina... | 12/01/2009 |
| 7599974 | Data processing apparatus and method for comparing floating point operands A data processing apparatus compares first and second floating point operands to produce a comparison result. For each floating point operand, a first component is derived from a predetermined number of MSBs of the fraction component which is less than the total num... | 10/06/2009 |
| 7593976 | Method and apparatus for finding the next free bit in a register The present invention provides a method and apparatus for finding the next free bit in a register, starting from a known pointer. The present invention breaks the N bits of a vector in a register into M parts, performs an AND operation to all bits of each part respe... | 09/22/2009 |
| 7587437 | Parallel efficiency calculation method and apparatus This parallel efficiency calculation method can be applied, even in a case where a load balance is not kept, to many parallel processing including a heterogeneous computer system environment, and quantitatively correlates a parallel efficiency with a load balance co... | 09/08/2009 |
| 7552154 | System and method for statistically separating and characterizing noise which is added to a signal of a machine or a system Method for finding the probability density function type and the variance properties of the noise component N of a raw signal S of a machine or a system, said raw signal S being combined of a pure signal component P and said noise component N, the method comprising:... | 06/23/2009 |
| 7539714 | Method, apparatus, and instruction for performing a sign operation that multiplies Method, apparatus, and program means for performing a sign and multiply operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location... | 05/26/2009 |
| 7533139 | Method and system for multithread processing of spreadsheet chain calculations Embodiments of the invention involve a method of concurrent processing of chain calculations using multiple processors each having a separate recalculation engine in a spreadsheet program. The operations basically include first determining a number of available proc... | 05/12/2009 |
| 7490118 | Expanding instruction set using alternate error byte Expanding the capacity of a fixed digital field using a unique number calculated from the digital field, such as an error code. Expansion is possible by calculating a new error code using a different algorithm. A recipient, upon not detecting the error code from the... | 02/10/2009 |
| 7475101 | Method and structure for producing high performance linear algebra routines using streaming A method (and structure) of improving at least one of speed and efficiency when executing a linear algebra subroutine on a computer having a memory hierarchical structure including at least one cache, the computer having M levels of caches and a main memory. Based o... | 01/06/2009 |
