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| Number | Title | Issue Date |
| 7430546 | Applications of an algorithm that mimics cortical processing An information processing system having neuron-like signal processors that are interconnected by synapse-like processing junctions that simulates and extends capabilities of biological neural networks. The information processing systems uses integrate-and-fire neuro... | 09/30/2008 |
| 7389208 | System and method for dynamic knowledge construction A system and method responsive to input stimuli is provided by incorporating a computer software program, hardware processing engine, or a specialized ASIC chip processor apparatus to capture concurrent inputs that are responsive to training stimulation, store a mod... | 06/17/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7352918 | Method and circuits for scaling images using neural networks An artificial neural network (ANN) based system that is adapted to process an input pattern to generate an output pattern related thereto having a different number of components than the input pattern. The system (26) is comprised of an ANN (27) and a ... | 04/01/2008 |
| 7349928 | System and method for identifying relationships between database records A system for identifying relationships between database records includes a memory operable to store a plurality of records comprising a first record and at least one second record. Each record comprises at least one of a plurality of tokens. The system also includes... | 03/25/2008 |
| 7343314 | System and method for scheduling and train control A scheduling system and method for moving plural objects through a multipath system described as a freight railway scheduling system. The scheduling system utilizes a cost reactive resource scheduler to minimize resource exception while at the same time minimizing t... | 03/11/2008 |
| 7340328 | Scheduling system and method A scheduling system and method for moving plural objects through a multipath system described as a freight railway scheduling system. The scheduling system utilizes a cost reactive resource scheduler to minimize resource exception while at the same time minimizing t... | 03/04/2008 |
| 7292723 | System for image analysis in a network that is structured with multiple layers and differentially weighted neurons Disclosed herein are systems and methods for facilitating the usage of an online workforce to remotely monitor security-sensitive sites and report potential security breaches. In some embodiments, cameras are configured to monitor critical civilian infrastruc... | 11/06/2007 |
| 7280989 | Phase-locked loop oscillatory neurocomputer A neural network computer (20) includes a weighting network (21) coupled to a plurality of phase-locked loop circuits (251-25N). The weighting network (21) has a plurality of weighting circuits (C11, . . . , C... | 10/09/2007 |
| 7277831 | Method for detecting time dependent modes of dynamic systems In a method for detecting the modes of a dynamic system with a large number of modes that each have a set α (t) of characteristic system parameters, a time series of at least one system variable x(t) is subjected to modeling, for example switch segmentation, so tha... | 10/02/2007 |
| 7272585 | Operation circuit and operation control method thereof A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascendin... | 09/18/2007 |
| 7266255 | Distributed multi-sample convolution A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the screen, a new design utilizes chips working in series. Each chip is resp... | 09/04/2007 |
| 7249115 | Network modelling According to a first aspect of the present invention there is provided a method of modelling a network comprising operating the network as a neural network and executing a neural network modelling algorithm on the network, whereby the network models its own response... | 07/24/2007 |
| 7246292 | Apparatus and method for bit pattern learning and computer product A computer calculates bit patterns of syndromes for all candidate bit patterns of reception words that are input in ECC-EOR circuits of a logic circuit. The bit patterns of the syndromes are stored as possible bit patterns. Request bit patterns are propagated when a... | 07/17/2007 |
| 7246129 | System and method for identifying relationships between database records A system for identifying relationships between database records includes a memory operable to store a plurality of records comprising a first record and at least one second record. Each record comprises at least one of a plurality of tokens. The system also includes... | 07/17/2007 |
| 7222002 | Vibration engine monitoring neural network object monitoring The present invention provides an aircraft engine vibration system that provides information about engine health. Embodiments of the present invention monitor for excessive vibration, monitor for bird strike, monitor for ice build up on the fan section, and monitor ... | 05/22/2007 |
| 7187737 | Data transmitting unit, data communicating apparatus and data communicating method In a transmitting apparatus 101, there are provided PLL circuit 601 for generating high-speed clock signals up to 2m times (m being a positive integer) from a basic clock signal, and a clock generating circuit 600 for generating a com... | 03/06/2007 |
| 7173470 | Clock sources and methods with reduced clock jitter Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized wi... | 02/06/2007 |
| 7155708 | Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a c... | 12/26/2006 |
| 7151472 | Reference voltage stabilization in CMOS sensors A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference voltage to an analog-to-digital converter (ADC) during a digitization operation. The reference voltage gener... | 12/19/2006 |
| 7143072 | Method and a system for calculating the values of the neurons of a neural network A neural network having layers of neurons divided into sublayers of neurons. The values of target neurons in one layer are calculated from sublayers of source neurons in a second underlying layer. It is therefore always possible to use for this calculation the same ... | 11/28/2006 |
| 7107252 | Pattern recognition utilizing a nanotechnology-based neural network A pattern recognition system, comprising a neural network formed utilizing nanotechnology and a pattern input unit, which communicates with the neural network, wherein the neural network processes data input via the pattern input unit in order to recognize data patt... | 09/12/2006 |
| 7069257 | Pattern recognition method for reducing classification errors A RBF pattern recognition method for reducing classification errors is provided. An optimum RBF training approach is obtained for reducing an error calculated by an error function. The invention continuously generates the updated differences of parameters in the lea... | 06/27/2006 |
| 7064994 | Dynamic memory throttling for power and thermal limitations In one embodiment, a memory controller is coupled to a memory subsystem and controls accesses to the memory subsystem. In addition, a temperature sensor is positioned to detect a temperature associated with the memory subsystem. In this embodiment, the memory contro... | 06/20/2006 |
| 7062476 | Student neural network A student neural network that is capable of receiving a series of tutoring inputs from one or more teacher networks to generate a student network output that is similar to the output of the one or more teacher networks. The tutoring inputs are repeatedly processed b... | 06/13/2006 |
| 7053895 | Image processing apparatus, image processing method, control program and recording medium An image processing apparatus which processes input image data of Y lines, each consisting of X pixels, using an SIMD processor, comprises a calculation unit including N (X>N>1, Y>N>1) elemental processors capable of parallel-operating; an input unit for dividing an... | 05/30/2006 |
| 7039619 | Utilized nanotechnology apparatus using a neutral network, a solution and a connection gap An apparatus for maintaining components in neural network formed utilizing nanotechnology is described herein. A connection gap can be formed between two terminals. A solution comprising a melting point at approximately room temperature can be provided, wherein the ... | 05/02/2006 |
| 7031969 | System and method for identifying relationships between database records A system for identifying relationships between database records includes a memory operable to store a plurality of records comprising a first record and at least one second record. Each record comprises at least one of a plurality of tokens. The system also includes... | 04/18/2006 |
| 7028017 | Temporal summation device utilizing nanotechnology A temporal summation device can be composed of one or more nanoconnections having an input and an output thereof, wherein an input signal provided to the input causes one or more of the nanoconnection to experience an increase in connection strength thereof over tim... | 04/11/2006 |
| 7027446 | Method and apparatus for set intersection rule matching A method and apparatus for of high-speed and memory efficient rule matching, the rule matching being performed on an m-dimensional universe with each dimension bound by a given range of coordinate values, and a set of rules that apply to an undetermined number of co... | 04/11/2006 |
| 7024363 | Methods and apparatus for contingent transfer and execution of spoken language interfaces A method for managing spoken language interface data structures and collections of user interface service engines in a spoken language dialog manager in a personal speech assistant. Interfaces, designed as part of applications, may by these methods be added to or re... | 04/04/2006 |
| 6995649 | Variable resistor apparatus formed utilizing nanotechnology A variable resistor apparatus includes a plurality of nanoparticles disposed between two terminals, wherein the plurality of nanoparticles provides an electrical resistance. An electric field applied to the plurality of nanoparticles across the two terminals results... | 02/07/2006 |
| 6957204 | Oscillatary neurocomputers with dynamic connectivity A neurocomputer (50) comprises n oscillating processing elements (60A, 60B, 60C, 60D and 60E) that communicate through a common medium (70) so that there are required only n connective junctions (80A, 80... | 10/18/2005 |
| 6951008 | Evidential reasoning system and method Computerized method and system for making decisions based on evidential reasoning are provided. The method allows for providing a model structure; including a plurality of processing nodes. Each of the processing nodes is coupled to receive a set of inputs to supply... | 09/27/2005 |
| 6947916 | IC for universal computing with near zero programming complexity A computing machine capable of performing multiple operations using a universal computing unit is provided. The universal computing unit maps an input signal to an output signal. The mapping is initiated using an instruction that includes the input signal, a weight ... | 09/20/2005 |
| 6947913 | Systems and methods for generating string correlithm objects In one aspect of the invention, a system for processing data includes a memory operable to store a plurality of correlithm objects. Each correlithm object includes a plurality of values defining a point in a particular space. The particular space is defined by a plu... | 09/20/2005 |
| 6842745 | Programmable chaos generator and process for use thereof A chaotic signal generator includes a set of elements connected together for generating chaotic signals. The connection scheme may correspond to the circuit generally referred to as Chua's circuit, particularly when implemented as a cellular neural network. Interpos... | 01/11/2005 |
| 6836767 | Pipelined hardware implementation of a neural network circuit In a first aspect, a pipelined hardware implementation of a neural network circuit includes an input stage, two or more processing stages and an output stage. Each processing stage includes one or more processing units. Each processing unit includes storage for weig... | 12/28/2004 |
| 6714924 | Computer-implemented neural network color matching formulation system A method and apparatus for color matching are provided, in which paint recipe neural networks are utilized. The color of a standard is expressed as color values. The neural network includes an input layer having nodes for receiving input data related to paint bases.... | 03/30/2004 |
| 6678670 | Non-integer order dynamic systems A circuit implementing a non-integer order dynamic system includes a neural network that receives at least one input signal and generates therefrom at least one output signal. The input and output signals are related to each by a non-integer order integro... | 01/13/2004 |
