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Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 7822698 | Spike domain and pulse domain non-linear processors A neural network has an array of interconnected processors, each processor operating either the pulse domain or spike domain. Each processor has (i) first inputs selectively coupled to other processors in the array of processors, each first input having an associate... | 10/26/2010 |
| 7274749 | Method and apparatus for the linearization of a radio frequency high-power amplifier The invention relates to a method for the linearization of a high-frequency high-capacity amplifier by means of adaptive digital predistortion of the input signals of the amplifier (5) by determining correctional values that are approximated from DESIRED send... | 09/25/2007 |
| 7272585 | Operation circuit and operation control method thereof A product-sum operation circuit includes a pulse width/digital conversion circuit (9) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit (4) which outputs, in descending or ascendin... | 09/18/2007 |
| 7130776 | Method and computer program product for producing a pattern recognition training set The present invention recites a method and computer program product for generating a set of training samples from a single ideal pattern for each output class of a pattern recognition classifier. A system equivalent pattern is generated for each of a plurality of cl... | 10/31/2006 |
| 7107108 | Controller and method of controlling an apparatus using predictive filters In the field of electronic or computerised control apparatuses, known methods of compensating for disturbance signals rely on less than ideal analytical or empirical models. There is provided a controller (200) or method of controlling which observes and lear... | 09/12/2006 |
| 7092923 | Synapse element with learning function and semiconductor integrated circuit device including the synapse element A synapse configured of an A-MOS transistor has a learning function and can implement high integration similar to that of a DRAM because of its simplified circuit configuration and compact circuit size. With the presently cutting-edge technology (0.15 μm CMOS), app... | 08/15/2006 |
| 7035835 | High-precision current-mode pulse-width-modulation circuit A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the cu... | 04/25/2006 |
| 6934405 | Address reading method An address reading method with processing steps controlled by parameters, in which free parameters which cannot be adapted by learning samples are to be automatically optimized. These parameters are therefore assigned costs. The value of free parameters which are ex... | 08/23/2005 |
| 6671678 | Multi-functional arithmetic apparatus with multi value states A multi-functional arithmetic apparatus with multi value-states comprise a gating array, which is composed of gating elements arranged in n row by m column. Each gating element has at least two input terminals and one output terminal, and has input value-... | 12/30/2003 |
| 6625588 | Associative neuron in an artificial neural network An associative artificial neuron and method of forming output signals of an associative artificial neuron includes receiving a number of auxiliary input signals; forming from the auxiliary input signals a sum weighted by coefficients and applying a non-li... | 09/23/2003 |
| 6539368 | Neural processor, saturation unit, calculation unit and adder circuit The present invention relates to the field of computer science and can be used for neural network emulation and digital signal processing. Increasing of the neural processor performance is achieved using the ability to change word lengths of results in pr... | 03/25/2003 |
| 6523018 | Neural chip architecture and neural networks incorporated therein The neural semiconductor chip first includes: a global register and control logic circuit block, a R/W memory block and a plurality of neurons fed by buses transporting data such as the input vector data, set-up parameters, etc., and signals such as the f... | 02/18/2003 |
| 6513023 | Artificial neural network with hardware training and hardware refresh A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accor... | 01/28/2003 |
| 6507828 | Neuron circuit and related techniques A neuron circuit including means for synaptic modification is described. The circuit emulates the electrical behaviors of the neuron membrane, dendrite, and synapse, using principles based on the actual biology. In one embodiment, the circuit is implement... | 01/14/2003 |
| 6505182 | Recognition engine with time referenced neurons Detection is implemented by a multiplier, a lookup table or other apparatus with two inputs, one of which typically receives an input signal from a sensor, and the other a reference or weighting factor W stored or generated locally. The detected value is ... | 01/07/2003 |
| 6456992 | Semiconductor arithmetic circuit A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input ... | 09/24/2002 |
| 6405184 | Process for producing fault classification signals A method for generating fault classification signals which identify faulty loops which develop in a multiphase energy supply network observed in the event of a fault from a protective device with a starting arrangement. To be able to generate such fault c... | 06/11/2002 |
| 5956702 | Time-series trend estimating system and method using column-structured recurrent neural network Each neural element of a column-structured recurrent neural network generates an output from input data and recurrent data provided from a context layer of a corresponding column. One or more candidates for an estimated value is obtained, and an occurrenc... | 09/21/1999 |
| 5781702 | Hybrid chip-set architecture for artificial neural network system A self-contained chip set architecture for ANN systems, based on back-propagation model with full-connectivity topology, and on-chip learning and refreshing, based on analog chip set technology providing self-contained synapse and neuron modules with faul... | 07/14/1998 |
| 5696883 | Neural network expressing apparatus including refresh of stored synapse load value information A self-organizable neural network expressing unit includes a plurality of neuron units electronically expressing nerve cell bodies, and a plurality of synapse expressing units electronically expressing synapses for coupling neuron units through programmed... | 12/09/1997 |
| 5680515 | High precision computing with charge domain devices and a pseudo-spectral method therefor The present invention enhances the bit resolution of a CCD/CID MVM processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive ... | 10/21/1997 |
| 5644253 | Multiple-valued logic circuit There are provided n operation circuits in a multiple-valued logic circuit which receives plural multiple-valued input logic signals corresponding to respective numeral values and outputs a multiple-valued output logic signal corresponding to a sum of the... | 07/01/1997 |
| 5634067 | Systolic array processor A systolic array processor is provided which is adapted to virtually constitute a number of analog type pipelining processors which operate in a parallel manner on an analog type shift register array such as a CCD or the like. The processor is composed of... | 05/27/1997 |
| 5600843 | Ring systolic array system for synchronously performing matrix/neuron computation using data transferred through cyclic shift register connected in cascade of trays A parallel data processing system comprises a plurality of data processing units each having at least one input and storing data of a matrix and a plurality of trays each having a first input and an output and for storing data of a vector, each of all or ... | 02/04/1997 |
| 5553197 | Devices for use in neural processing A device for use in neural processing comprises a plurality of probabilistic RAMs (pRAMs). The output of the pRAMs are connected in common to means for accumulating their output signals and for decaying the result of the accumulation. A thresholding circu... | 09/03/1996 |
| 5479578 | Weighted summation circuitry with digitally controlled capacitive structures An array of weighted summation circuits, N in number, each generate a weighted sum response to the same plurality of input signals, M in number. Each weighted summation circuit includes at least one corresponding capacitive element for determining the wei... | 12/26/1995 |
| 5475794 | Semiconductor neural network and operating method thereof A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into ... | 12/12/1995 |
| 5412256 | Neuron for use in self-learning neural network A neuron for use in a self-learning neural network comprises a current input node at which a plurality of synaptic input currents are summed using Kirchoff's current law. The summed input currents are normalized using a coarse gain current normalizer. The... | 05/02/1995 |
| 5396581 | Semiconductor neural network and operating method thereof A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into ... | 03/07/1995 |
| 5355438 | Weighting and thresholding circuit for a neural network An analog circuit which performs weighting and thresholding for a neural network. Each neuron of the neural network includes an operational amplifier receiving an input signal, the output of which is connected to a transistor. The transistor conducts only... | 10/11/1994 |
| 5319738 | Neural network device This invention has an object to provide a practical neural network device. The first neural network device of this invention comprises an input circuit for performing predetermined processing of external input information and generating an input signal, a... | 06/07/1994 |
| 5295091 | Analog implementation of a pattern classifier A method of and system for classifying a pattern wherein there is provided a node, the negative of a predetermined threshold signal is applied to the node, a plurality of digital signals in parallel, is provided the digital signals are converted to analog... | 03/15/1994 |
| 5293457 | Neural network integrated circuit device having self-organizing function An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circu... | 03/08/1994 |
| 5274746 | Coupling element for semiconductor neural network device A neural network device includes internal data input lines, internal data output lines, coupling elements provided at the connections of the internal data input lines and the internal data output lines, word lines each for selecting one row of coupling el... | 12/28/1993 |
| 5274743 | Learning system for a neural net of a suitable architecture, physically insertable in the learning process The subject of the invention is a learning system for a neural net physically insertable in the learning process, which comprises a detecting member for presenting to said neural net the basic information set that said neural net has to learn in order to ... | 12/28/1993 |
| 5264734 | Difference calculating neural network utilizing switched capacitors A difference calculating neural network is disclosed having an array of synapse cells arranged in rows and columns along pairs of row and column lines. The cells include a pair of floating gate devices which have their control gates coupled to receive one... | 11/23/1993 |
| 5255349 | Electronic neural network for solving "traveling salesman" and similar global optimization problems This invention is a novel high-speed neural network based processor for solving the "traveling salesman" and other global optimization problems. It comprises a novel hybrid architecture employing a binary synaptic array whose embodiment incorporates the f... | 10/19/1993 |
| 5235672 | Hardware for electronic neural network This application discloses hardware suitable for use in a neural network system. It makes use of Z-technology modules, each containing densely packaged electronic circuitry. The modules provide access planes which are electrically connected to circuitry l... | 08/10/1993 |
| 5224066 | Method and apparatus for parallel implementation of neural networks Long and short term memory equations for neural networks are implemented by means of exchange of signals which carry information in the form of both binary and continuously modulated energy emissions. In one embodiment, array of parallel processors exhibi... | 06/29/1993 |
| 5212766 | Neural network representing apparatus having self-organizing function A neutral network representing apparatus includes a plurality of neuron expressing units and a plurality of synapse load expressing units. Each of the synapse load expressing units couples two neuron expressing units through a synapse load which is specif... | 05/18/1993 |
