Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 6061511 | Reconstruction engine for a hardware circuit emulator A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input ... | 05/09/2000 |
| 6052524 | System and method for simulation of integrated hardware and software components A system and methods are provided to design, verify and develop simulated hardware and software components for a desired electrical device. The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycl... | 04/18/2000 |
| 6051030 | Emulation module having planar array organization Emulation modules containing an increased number of emulation processors are logically reconfigured into a plurality of planes which are interconnected by means of multiplexors to avoid I/O pinout complexities introduced by the increase in the number of e... | 04/18/2000 |
| 6028996 | Method and apparatus for virtualizing system operation A method and apparatus for emulating operation of a complex circuit within a system, thereby creating a virtual system, is achieved within a system that includes a central processing unit (CPU), system memory, at least one functional module, and an emulat... | 02/22/2000 |
| 6014697 | Method and apparatus for automatically populating a network simulator tool Method and apparatus for automatically populating a network simulation tool database with network topology and/or traffic information. A topology extraction tool is provided for reading the topology and traffic information in a network management system d... | 01/11/2000 |
| 6009264 | Node coordination using a channel object and point-to-point protocol A method, apparatus, and article of manufacture for coordinating a plurality of sub-tasks performed by a group of nodes of a parallel processor computer system. An application subdivides a function into the plurality of sub-tasks and assigns the sub-tasks... | 12/28/1999 |
| 6006022 | Cross-linked development and deployment apparatus and method A cross-linked development and deployment system that links system design, simulation, real-time emulation, integration, and in-system verification to system implementation in the field, creating final products that are field programmable systems on print... | 12/21/1999 |
| 5999725 | Method and apparatus tracing any node of an emulation A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence ide... | 12/07/1999 |
| 5991533 | Verification support system A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulatio... | 11/23/1999 |
| 5978584 | Debugging apparatus for debugging a program by changing hardware environments without changing program operation state A debugging apparatus is disclosed which verifies a program to be embedded into a target machine by running the program in an environment which is one or the target machine, an emulator, and a simulator. Each environment includes operation state informati... | 11/02/1999 |
| 5960190 | In-circuit emulation system with minimal impact on target environment An ICE system for emulating a device includes an EPROM storing control code, at least one RAM storing user code and data, a processor alternatively executing the control code and user code, and memory map switch logic dynamically switching the memory addr... | 09/28/1999 |
| 5960191 | Emulation system with time-multiplexed interconnect A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of re... | 09/28/1999 |
| 5943490 | Distributed logic analyzer for use in a hardware logic emulation system A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of re... | 08/24/1999 |
| 5940603 | Method and apparatus for emulating multi-ported memory circuits A memory design is implemented in static memory circuits having a plurality of bidirectional access ports, wherein each port is configured for read or write access. The memory design defines initial contents, depth, width, and bank selection in the memory... | 08/17/1999 |
| 5898862 | Method for configuring an integrated circuit for emulation with optional on-chip emulation circuitry An integrated circuit is provided having a core circuit for performing a plurality of functions, a first pad for receiving an emulator output signal, a pulldown device connected to said first pad, a first logic circuit having an input connected to said fi... | 04/27/1999 |
| 5884066 | Method and apparatus for a trace buffer in an emulation system A tracing method and apparatus for a digital emulation system. The invention allows trace information to be obtained during the emulation of a digital circuit that includes a clock signal. Input signal states are sensed and stored each clock cycle. The in... | 03/16/1999 |
| 5872953 | Simulating circuit design on a circuit emulation system A circuit transformation software module incorporating the teachings of the present invention is provided to an otherwise conventional emulation system. The circuit transformation software module takes a circuit design as input and transforms it into a "n... | 02/16/1999 |
| 5857094 | In-circuit emulator for emulating native clustruction execution of a microprocessor An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared amo... | 01/05/1999 |
| 5848264 | Debug and video queue for multi-processor chip A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue ... | 12/08/1998 |
| 5822226 | Hardware system verification environment tool A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor ... | 10/13/1998 |
| 5822564 | Checkpointing in an emulation system A method and apparatus for outputting a current state of a real-time circuit emulator. When the emulator is set to a predetermined state, it checkpoints the contents of certain memory and registers at the time it enters the predetermined state. The output... | 10/13/1998 |
| 5805865 | Semiconductor device A microcomputer chip is formed with a CPU core, a peripheral circuit, a built-in ROM, and a built-in RAM. An emulation functional chip is formed with an emulation control circuit for controlling the whole process of emulation. First electrode pads formed ... | 09/08/1998 |
| 5802347 | Emulator with function for detecting illegal access to special function register An interface section controls a communication interface between an in-circuit emulator and a host computer. A CPU core board for emulating a CPU core section of the computer has therein a special function register illegal access detector which stores devi... | 09/01/1998 |
| 5802573 | Method and system for detecting the issuance and completion of processor instructions A method and apparatus for verifying memory coherency of a simulated computer system. A verification logic unit is used for detecting the issuance of load and store instructions from the simulated system. Targets (registers or memory locations) representi... | 09/01/1998 |
| 5798645 | Hardware emulations system with delay units The invention relates to an electronic hardware ASIC (Application Specific Integrated Circuit) prototyper permitting the emulation of integrated circuits or ASICs, so that testing of the component to be generated is possible in the later hardware environm... | 08/25/1998 |
| 5790833 | Integrated circuit, having microprocessor and telephony peripheral circuitry, having capability of being placed in partial emulation mode An in-circuit emulation capability mode incorporated in an integrated circuit. The in-circuit emulation capability mode disables the microcontroller of the integrated circuit and allows use of an external in-circuit emulator device to test and debug the i... | 08/04/1998 |
| 5790832 | Method and apparatus for tracing any node of an emulation A method and apparatus for tracing any node in an emulator, including hidden nodes of a circuit design, includes maintaining a correspondence between physically observable nodes and hidden nodes of the circuit design being emulated. The correspondence ide... | 08/04/1998 |
| 5687371 | Selection from a plurality of bus operating speeds for a processor bus interface during processor reset A method and apparatus for providing an interface from a processor to a bus. The interface is capable of operating at a speed selected from a plurality of speeds. An execution unit is coupled to a register file. The register file comprises a plurality of ... | 11/11/1997 |
| 5680542 | Method and apparatus for synchronizing data in a host memory with data in target MCU memory A copy of data in a Host Computer is synchronized with a version located in Shared Memory in a Modular Development System (MDS). Whenever a change in one or more bits in a Line of Data in Shared Memory are detected, a MDS Line Dirty Flag is checked. If th... | 10/21/1997 |
| 5673419 | Parity bit emulator with write parity bit checking A computer system includes a parity bit emulator circuit which generates a parity bit to be associated with a data byte output by a signal in-line memory module (SIMM) to a CPU. Each parity bit emulator monitors four consecutive write cycles to determine ... | 09/30/1997 |
| 5655111 | In-circuit emulator An in-circuit emulator comprises a pod portion mounted with a microcomputer equivalent to a target microcomputer and an emulator main body which offers a debug function. There are provided between the pod portion and the emulator main body a common bus to... | 08/05/1997 |
| 5640542 | On-chip in-circuit-emulator memory mapping and breakpoint register modules A pair of In-Circuit-Emulator modules are embedded within a microprocessor to implement parts of an In-Circuit-Emulator system. A first In-Circuit-Emulator module, the In-Circuit-Emulator memory mapping module, maps specified physical addresses into a deb... | 06/17/1997 |
| 5630102 | In-circuit-emulation event management system A microprocessor system utilizing an in-circuit emulator (ICE) to aid in testing and debugging by an external emulator. The microprocessor operates in two modes. One mode is emulation mode in which the microprocessor outputs trace information for allowing... | 05/13/1997 |
| 5574892 | Use of between-instruction breaks to implement complex in-circuit emulation features A processor uses between-instruction in-circuit emulation breaks to implement complex in-circuit emulation features. The processor uses a bit in hardware that triggers a between-instruction break to in-circuit emulation to permit complex in-circuit emulat... | 11/12/1996 |
| 5572710 | High speed logic simulation system using time division emulation suitable for large scale logic circuits A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets. The system includes: a host computer having data of the simulation target divided into... | 11/05/1996 |
| 5546566 | Emulation system for microcomputer An emulation system for emulating an application specific integrated circuit (ASIC) type microcomputer including a central processing unit, a user specific peripheral function unit and a user specific logic circuit, which are integrated together on a sing... | 08/13/1996 |
| 5544307 | Microcomputer development support system operable with only background monitor and without cache replacement A microcomputer development support system for a microprocessor, includes an instruction substituting circuit tracing a memory access performed by the microprocessor and substituting a predetermined branch instruction for an instruction which is read out ... | 08/06/1996 |
| 5539907 | System for monitoring computer system performance A program for monitoring computer system performance includes a collection of source code modules in the form of a high level language. Each of the source code modules is compiled into a corresponding object code module. The object code modules are transl... | 07/23/1996 |
| 5539901 | Method and apparatus for system management mode support for in-circuit emulators An in-circuit emulation unit with a probe implemented on a microprocessor whilst in emulation upon entering or leaving system management mode. The present invention is used on a microprocessor in a target computer system. The present invention offers the ... | 07/23/1996 |
| 5530804 | Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referre... | 06/25/1996 |
