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| Number | Title | Issue Date |
| 6539347 | Method of generating a display for a dynamic simulation model utilizing node and link representations A method of generating a display, or representation, of a simulation model within a graphical user interface (GUI) is described. The simulation model includes a number of objects, which may include state, function, link and modifier objects. The method co... | 03/25/2003 |
| 6529862 | Method and apparatus for dynamic management of translated code blocks in dynamic object code translation In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies wheth... | 03/04/2003 |
| 6516295 | Method and apparatus for emulating self-modifying code In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies wheth... | 02/04/2003 |
| 6507809 | Method and system for simulating performance of a computer system A high-speed performance simulation method and system for simulating the performance of a large-scaled system such as a parallel computer. In implementation, the large-scaled system is divided into subsystems or partial units and the divided subsystems ar... | 01/14/2003 |
| 6507808 | Hardware logic verification data transfer checking apparatus and method therefor An apparatus and method for hardware logic verification data transfer checking are implemented. Data for transfer is generated in response to a decoded bus transaction instruction using a pseudorandom number generator. The seed for the generator includes ... | 01/14/2003 |
| 6502181 | Method and apparatus for an enhanced processor A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiri... | 12/31/2002 |
| 6480818 | Debugging techniques in a multithreaded environment A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a b... | 11/12/2002 |
| 6480952 | Emulation coprocessor A computer system employing a host processor and an emulation coprocessor. The host processor includes hardware configured to execute instructions defined by a host instruction set architecture, while the emulation coprocessor includes hardware configured... | 11/12/2002 |
| 6480845 | Method and data processing system for emulating virtual memory working spaces In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real add... | 11/12/2002 |
| 6473726 | Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming in... | 10/29/2002 |
| 6456962 | Interface to network protocol software to support hardware acceleration of critical functions LAN interface logic (33) receives frames from a LAN segment (32), and frame transport logic (40, 54, 56) transfers frames to and from an ATM network. Forwarding logic (36) is used to (i) determine whether a mapping between a destination address (DA) and a... | 09/24/2002 |
| 6453278 | Flexible implementation of a system management mode (SMM) in a processor A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "... | 09/17/2002 |
| 6449755 | Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist.... | 09/10/2002 |
| 6449712 | Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or... | 09/10/2002 |
| 6445974 | CAD-neutral application programming interface Apparatus and method for a computer-aided design (CAD) system for dynamically switching from one CAD platform to another CAD platform. The invention includes building a library of generic CAD functions, each for directing a graphical manipulation process.... | 09/03/2002 |
| 6438514 | Generation of a system model A computer is operated to generate electronic data defining a system model by loading into the computer a class definition defining instructions which are processed by the system, the definition including a set of functional methods to which the instructi... | 08/20/2002 |
| 6438432 | Process for the protection of stored program controls from overwriting A method is provided for protecting stored-program control systems, in particular in motor vehicles, which offers a software protection system for programming. A programming routine for programming by an external device is subdivided into segments in such... | 08/20/2002 |
| 6434660 | Emulating one tape protocol of flash memory to a different type protocol of flash memory A flash memory controller translates between manufacturer-specific protocols to allow the flash memories of one manufacturer to be used transparently in a host system programmed for the memory devices of different manufacturer. According to the invention,... | 08/13/2002 |
| 6427000 | Performing automated testing using automatically generated logs The present invention performs automated testing on service applications using automatically generated logs, so that new testing applications do not need to be created for each new release of a service application. The invention further provides for testi... | 07/30/2002 |
| 6424934 | Packet classification state machine having reduced memory storage requirements A programmable state machine comprising a program memory and a processor is disclosed wherein the state machine operates with the processor accessing the program memory one or fewer times per state transition and wherein the data stored within the program... | 07/23/2002 |
| 6422474 | N-space indexing of digital data representations using physical tags A system for N-space navigation of digital data sets comprising an electronic tag having a digitally readable identifier, an electronic tag reader configured to read the identifier of the electronic tag, and a computing system connected to the electronic ... | 07/23/2002 |
| 6421635 | Method and apparatus for handling asynchronous signals while emulating system calls The invention determines whether any asynchronous signals are pending and then delivers any such pending signals to the emulated application before the control is transferred to the operating system. A first mechanism sets a global flag, and checks to det... | 07/16/2002 |
| 6415379 | Method and apparatus for maintaining context while executing translated instructions A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a ... | 07/02/2002 |
| 6415436 | Mechanism for cross validating emulated states between different emulation technologies in a dynamic compiler The inventive mechanism compares system states resulting from emulation of the same block of source code by different emulation technologies within a dynamic compiler. A set of initial conditions, parameters of the system state S1, preceding any emulation... | 07/02/2002 |
| 6405300 | Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor One embodiment of the present invention provides a system that efficiently emulates sub-instructions in a very long instruction word (VLIW) processor. The system operates by receiving an exception condition during execution of a VLIW instruction within a ... | 06/11/2002 |
| 6389384 | Servo processor code evaluation using a virtual disc drive Method and apparatus for evaluating programming used by a programmable processor device in a disc drive to carry out servo control of a head with respect to a rotatable disc. The programming is first generated as a series of instructions executable by the... | 05/14/2002 |
| 6385718 | Computer system and method for executing interrupt instructions in operating modes A computer system including a given microprocessor specifically designed to operate in a virtual operating mode allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-task... | 05/07/2002 |
| 6385566 | System and method for determining chip performance capabilities by simulation A system and method are disclosed in which multiple components make demands on a common resource, such as a common memory. When it is desirable to change certain operating parameters of a component, an algorithm is performed which determines whether the c... | 05/07/2002 |
| 6385567 | Program-module substitution in a program loader for multiple-platform emulation A single program loader loads program modules for multiple platforms in an emulation environment. A name list has entries each containing the name of a module for one platform and the name of a corresponding module for another platform. The loader identif... | 05/07/2002 |
| 6366877 | Method and device for emulation of peripheral input/output (I/O) controller of a computer system A reception/transmission circuit 20 receives and transmits data from and to a keyboard 16 and mouse 18. An output buffer 42 temporarily stores data from the keyboard 16 and mouse 18 while an input buffer 44 temporarily stores data from BIOS 100 and an int... | 04/02/2002 |
| 6366876 | Method and apparatus for assessing compatibility between platforms and applications Embodiments of the invention can be used to assess whether a software application is compatible with an operating platform. A specification that describes the operating platform is generated using a definitional language. The specification identifies the ... | 04/02/2002 |
| 6366878 | Circuit arrangement for in-circuit emulation of a microcontroller A circuit configuration allowing for in-circuit emulation, comprising a memory containing an operating program; and a first and second microcontrolller. Each microcontroller has a computer core, at least five external connection ports, and a setable conne... | 04/02/2002 |
| 6363336 | Fine grain translation discrimination A method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the step... | 03/26/2002 |
| 6360194 | Different word size multiprocessor emulation In the emulation of a target system utilizing a multiprocessor (12) host system (10) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memor... | 03/19/2002 |
| 6356995 | Microcode scalable processor A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables... | 03/12/2002 |
| 6356997 | Emulating branch instruction of different instruction set in a mixed instruction stream in a dual mode system A dual mode branch and branch control system and method is disclosed for accommodating a processor that can operate in either of two operating modes, each using a different type of branch instruction. In a first instruction set, a first type branch instru... | 03/12/2002 |
| 6356862 | Hardware and software co-verification employing deferred synchronization Hardware and software of a system is co-verified with synchronization events generated in the respective hardware and software verifications being accumulated and provided to the other verification on a periodic basis. The faster verification is halted to... | 03/12/2002 |
| 6339752 | Processor emulation instruction counter virtual memory address translation When emulating a Target architecture on a Host system having a different architecture, virtual-to-real address translation is typically expensive in terms of computer cycles. The cost for translating addresses for instruction fetches can be significantly ... | 01/15/2002 |
| 6330528 | Method of terminating temporarily unstoppable code executing in a multi-threaded simulated operating system An operating system is simulated to run in conjunction with a native operating system, allowing processes, particularly multi-threaded processes, originally developed for the simulated operating system to be ported to the environment of the native operati... | 12/11/2001 |
| 6327676 | Test equipment Apparatus for testing a data storage system. The system includes an interface adapted for disposition between a host computer and a disk drives. The interface has a controller and an addressable memory interconnected through a bus. The system operates asy... | 12/04/2001 |
