Class 703/19 - Timing

Subclass of Class 703 - Data processing: structural design, modeling, simulation, and emulation
Definition: Subject matter wherein the timing delay of the electrical
No. of patents: 418
Last issue date: 05/22/2012

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Number	Title	Issue Date
6275784	Design method of routing signal lines between circuit blocks for equalizing characteristics of circuit blocks and semiconductor integrated circuit device designed therethrough An integrated circuit device is layoutted on a semiconductor chip, and signal lines are routed between circuit blocks to be integrated on the semiconductor chip, wherein a conductive line is branched from another conductive line passing over one of certai...	08/14/2001
6263303	Simulator architecture An simulator particularly suited for simulating the hardware/software behavior of embedded systems. The architecture of the simulator permits the hardware and software systems to be modeled as modules with well characterized behaviors. A concise module de...	07/17/2001
6263301	Method and apparatus for storing and viewing data generated from a computer simulation of an integrated circuit A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of si...	07/17/2001
6263302	Hardware and software co-simulation including simulating the cache of a target processor A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is ...	07/17/2001
6237127	Static timing analysis of digital electronic circuits using non-default constraints known as exceptions Exceptions allow a circuit designer, working with a circuit synthesis system, to specify certain paths through the circuit to be synthesized as being subject to non-default timing constraints. The additional information provided by the exceptions can allo...	05/22/2001
6230294	Transient analysis device for analog/digital mixed circuit and analysis method thereof A transient analysis device in which a simulation executing unit uses a first net list produced by a net list producing unit to measure a settling time of an analog/digital mixed circuit to be analyzed, after a dummy pulse parameter setting unit sets a pa...	05/08/2001
6230115	Simulator, simulation method, and medium having simulation program recorded, taking account of timing in electronic component and signal transmission through transmission line on printed-circuit board A simulator includes a timing simulation section executing timing simulation for a logic circuit of an electronic component, a time management section extracting logical operation time at an output terminal of the electronic component from a result of the...	05/08/2001
6230302	Method and system for performing timing analysis on an integrated circuit design A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain mo...	05/08/2001
6223141	Speeding up levelized compiled code simulation using netlist transformations Delay-independent cycle-based logic simulation of synchronous digital circuits with levelized compiled code simulation has substantially increased speed. Sweep, eliminate, and factor reduce the number of literals. The use of cofactoring, a register alloca...	04/24/2001
6216255	Computer-aided logic circuit designing apparatus computer-aided logic circuit designing system, and computer-aided logic circuit designing method A computer-aided logic circuit designing apparatus in which data on a plurality of circuits is stored in a database, the data on a plurality of circuits is read out therefrom and combined by a net list-RTL description combining section, a clock system por...	04/10/2001
6212490	Hybrid circuit model simulator for accurate timing and noise analysis A system and method for analyzing timing and noise effects in a hybrid circuit which contains a plurality of electrical components. The timing and noise effects for the hybrid circuit are generated by simulating electrical conditions within a hybrid circu...	04/03/2001
6195623	Time-frequency method and apparatus for simulating the initial transient response of quartz oscillators A time-frequency method and apparatus are disclosed for simulating the initial transient response of quartz oscillators. An original system of differential algebraic equations that characterize a quartz oscillator are reformulated using a system of well-d...	02/27/2001
6185723	Method for performing timing analysis of a clock-shaping circuit A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspo...	02/06/2001
6185518	Method and system for logic design constraint generation A system and method for generating design constraints for a logic synthesized block from timing analysis of the block. A timing analysis of logic described in software is performed for each of various operating modes of a circuit in which the logic is use...	02/06/2001
6173432	Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay...	01/09/2001
6169968	Apparatus and method for estimating performance integrated circuit The invention provides an apparatus and a method for accurately and rapidly estimating a performance of an integrated circuit in the design at a register transfer level. A parsing member converts an HDL description of the integrated circuit at the registe...	01/02/2001
6167364	Methods and apparatus for automatically generating interconnect patterns in programmable logic devices Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description...	12/26/2000
6161081	Simulation model for a digital system A simulation model for a digital system comprises a number of functional units, interconnected by a number of interface units for transmitting messages between the functional units. Each interface unit includes a mechanism for automatically composing and ...	12/12/2000
6138267	Reliability verification device for detecting portion of design that may cause malfunction of semiconductor integrated circuit and its verifying method A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a t...	10/24/2000
6131181	Method and system for identifying tested path delay faults The present invention relates to a method and system for identifying tested path-delay faults in integrated circuits. A path status graph is generated to represent the detected status of simulated path-delay faults. The path status graph includes vertices...	10/10/2000
6128769	Method for analyzing and efficiently reducing signal cross-talk noise In the present invention, a method is provided for analyzing signal noise caused by cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. This method comprises ...	10/03/2000
6110219	Model for taking into account gate resistance induced propagation delay When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resi...	08/29/2000
6093212	Method for selecting operation cycles of a semiconductor IC for performing an IDDQ test by using a simulation Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly...	07/25/2000
6090152	Method and system for using voltage and temperature adders to account for variations in operating conditions during timing simulation A method and system for predicting the sensitivity of the integrated circuit logic cell timing performance to variations in voltage and temperature. Rather than using the prior art approach of multiplicative derating factors to model voltage and temperatu...	07/18/2000
6090150	Method of designing clock wiring and apparatus for implementing the same In laying out the wiring of an LSI, PWB or the like, based on the logical connection information, layout result information, delay analyzing information or the like, the delay time margins for the entire path is evaluated by means of a delay analyzing mea...	07/18/2000
6086621	Logic synthesis constraints allocation automating the concurrent engineering flows A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit....	07/11/2000
6085307	Multiple native instruction set master/slave processor arrangement and method thereof A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache fo...	07/04/2000
6080201	Integrated placement and synthesis for timing closure of microprocessors One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semico...	06/27/2000
6074429	Optimizing combinational circuit layout through iterative restructuring Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from t...	06/13/2000
6066177	Method and apparatus for calculating delay for logic circuit and method of calculating delay data for delay library In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and th...	05/23/2000
6063130	Circuit simulation method In a circuit simulation method, circuit information of an electronic circuit to be simulated is inputted, and whether or not a linear circuit element circuit included in the electronic circuit is passive, is discriminated. For this discrimination, an indu...	05/16/2000
6059835	Performance evaluation of processor operation using trace pre-processing A processor performance evaluation system and method provides a method of model decomposition and trace attribution by first decomposing a full pipelined model of the entire system into a main model and one or more additional sub-models, such that it is p...	05/09/2000
6053950	Layout method for a clock tree in a semiconductor device A clock signal distribution circuit has a clock tree configuration. In the layout of the clock tree, a standard clock tree is prepared having a route buffer, a plurality of intermediate stage buffer cells and a plurality of last stage buffer cells connect...	04/25/2000
6052523	Method of transient analysis considering time steps and a device for implementing the method Upon a transient analysis simulation, if a time step between calculation points is relatively small, a forced quit error occurs, which leads to deterioration of development efficiency. A voltage vn at a calculation point tn is obtain...	04/18/2000
6052524	System and method for simulation of integrated hardware and software components A system and methods are provided to design, verify and develop simulated hardware and software components for a desired electrical device. The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycl...	04/18/2000
6041169	Method and apparatus for performing integrated circuit timing including noise A method, apparatus, and article of manufacture for performing timing analysis on an integrated circuit, which run a high level chip timing tool with initial RC delays for all nets of the integrated circuit; determine a list of time-critical nets from a t...	03/21/2000
6028995	Method of determining delay in logic cell models A logic-cell model accounts for nonlinear effects in determining propagation delay, thereby providing improved accuracy as compared to existing models, particularly when rise/fall times exceed several nanoseconds. Given a logic cell of the type wherein de...	02/22/2000
6023568	Extracting accurate and efficient timing models of latch-based designs A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used f...	02/08/2000
6018623	Method and system for determining statistically based worst-case on-chip interconnect delay and crosstalk A method and system of determining circuit performance-related characteristics, particularly delay and crosstalk, of interconnects includes defining a number of process variables which exhibit Gaussian distributions with respect to geometrical variances. ...	01/25/2000
6014510	Method for performing timing analysis of a clock circuit A method for accurately and precisely computing the output signal transition times in a clock distribution, or buffering, network of a data processing system is provided herein. This methodology may be implemented in transistor-level static timing analysi...	01/11/2000

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Class 703/19 - Timing