Class 703/19 - Timing

Subclass of Class 703 - Data processing: structural design, modeling, simulation, and emulation
Definition: Subject matter wherein the timing delay of the electrical
No. of patents: 418
Last issue date: 05/22/2012

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Number	Title	Issue Date
5359535	Method for optimization of digital circuit delays A method for optimization of delay times in a digital circuit. The method comprises selecting a logic gate (12), and constructing a model (35) which predicts the delay time (27) of the logic gate (12). Varying the parameters which control the model to mor...	10/25/1994
5355321	Static timing verification A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common ...	10/11/1994
5293327	Method of logic circuit simulation A method of logic simulation includes the steps of reading delay time of a logic element itself calculated in advance, converting output logic value of the logic element to a voltage value, forming a circuit equation based on connection information of an ...	03/08/1994
5278769	Automatic logic model generation from schematic data base An automatic logic-model generation system operates on a schematic database and produces logic models incorporating accurate timing information. A verification process is also performed whereby the model is automatically verified for accuracy....	01/11/1994
5274568	Method of estimating logic cell delay time A method for approximating the delay time of an excitation through a logic cell using the summation of a base delay, which is a function of delay coefficients for the cell and the total output load capacitance of the cell, and a rise/fall time correction,...	12/28/1993
5235521	Reducing clock skew in large-scale integrated circuits In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting...	08/10/1993
5212782	Automated method of inserting pipeline stages in a data path element to achieve a specified operating frequency According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an the equation such as: Ds =Db Nb +C whe...	05/18/1993
5210700	Automatic delay adjustment for static timing analysis Delay analysis in logic simulation is enhanced by providing, in a simulation model of a logic circuit, a timing delay tag on each circuit path connecting the output of a first with the input of the second circuit element. Each circuit leg is given a delay...	05/11/1993
5195024	Programmable controller Disclosed herein is a programmable controller comprising a central processing unit (CPU) and a delay element. The CPU operates on simulated input information in accordance with a sequence program. The result of the operation by the CPU is sent to the dela...	03/16/1993
5175843	Computer-aided design method for restructuring computational networks to minimize shimming delays A computer-aided design method for restructuring computational networks to minimize latency and shim delay, suitable for use by a silicon compiler. Data-flow graphs for computational networks which use trees of operators, each performing associative and c...	12/29/1992
5168563	Various possible execution paths measurement and analysis system for evaluating before writing source codes the efficiency performance of software designs A software engineering tool is disclosed which enables the efficiency and performance of a program design to be evaluated prior to the time the program is written into code. Every possible path that can be followed in the implementation of the program is ...	12/01/1992
5095454	Method and apparatus for verifying timing during simulation of digital circuits A digital circuit simulation method and apparatus provide for critical path timing analysis of digital circuitry using a hybrid path tracing method. The hybrid path tracing performs path tracing when, for example, simulation values change at designated in...	03/10/1992
5077676	Reducing clock skew in large-scale integrated circuits In a system of digital chips, the time delay in all clock trees is equalized by equalizing the delay through each level of all trees. The level delays are equalized by adjusting the capacitance of terminators in each net at each level, and/or by adjusting...	12/31/1991
5010493	Load distribution method A load distribution method in which loads are divided into groups and each of a plurality of input pins of integrated circuits of a load is wired continuously with one stroke of a signal transmission line in a sequence from a driving output pin in each gr...	04/23/1991
4907180	Hardware switch level simulator for MOS circuits A hardware switch level simulator for LSI/VLSI MOS circuits capable of simulating circuits with pass transistors and performing timing analysis. The simulator has a stack memory containing lists of nodes to be operated on, a solve unit having programmed l...	03/06/1990
4827427	Instantaneous incremental compiler for producing logic circuit designs A computer aided logic design system for instantaneously compiling circuit component entries into a schematic model which provides immediate simulation of each entry or deletion into the electronic circuit schematic. The system includes software for proce...	05/02/1989
4763288	System for simulating electronic digital circuits A simulation system for visual signal processing circuits is presented which provides a detailed, pixel level analysis of the timing while actually performing the simulation at the frame level. Input to the circuit is the form of images captured by a vide...	08/09/1988
4656580	Logic simulation machine An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconne...	04/07/1987

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Class 703/19 - Timing