Class 703/19 - Timing

Subclass of Class 703 - Data processing: structural design, modeling, simulation, and emulation
Definition: Subject matter wherein the timing delay of the electrical
No. of patents: 418
Last issue date: 05/22/2012

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Number	Title	Issue Date
8185371	Modeling full and half cycle clock variability A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities...	05/22/2012
8176461	Design-specific performance specification based on a yield for programmable integrated circuits A method for generating a design-specific timing specification includes inputting a first timing specification of a target device corresponding to a first timing yield. The first timing specification contains timing delays of elements located in at least first and s...	05/08/2012
8171442	Method and system to at least partially isolate nets A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net...	05/01/2012
8131528	Reporting delay using visual indicators in a model Exemplary embodiments report delay incurred in a model. Exemplary embodiments identify an incurred delay that is related to a graphical affordance in the model and generate a visual indicator associated with the graphical affordance in the model. The visual indicato...	03/06/2012
8121827	Efficient presentation of functional coverage results Apparatus for presentation of functional coverage, including one or more processors and a memory, wherein the memory stores software instructions including instructions for representing a set of attributes of a design under test as a multi-dimensional cross-product ...	02/21/2012
8086976	Methods for statistical slew propagation during block-based statistical static timing analysis Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew ...	12/27/2011
8082140	Parametric analysis of real time response guarantees on interacting software components A system and method for providing control timing for a vehicle system at the design level. The method includes defining component timing specifications in a parametric form at a system level and at a sub-system level; mathematically representing the timing specifica...	12/20/2011
8079006	Simulation method and computer-readable storage medium storing program for causing computer to analyze circuit operation using cell characteristics affected by environment A simulation method, to be implemented in a computer, carries out a simulation of a semiconductor integrated circuit. The simulation method carries out a layout analysis based on layout data of a circuit formed by cells and stores values of layout parameters obtaine...	12/13/2011
8073670	Method for calculating delay time, program for calculating delay time and device for calculating delay time A data row of delay time ratio coefficient (hereinafter referred to as DMAG value) is selected from a delay information library (D2) (S4) for every circuit cell in a use condition range of a logic circuit, and the minimum value or/and maximum value of ...	12/06/2011
8065645	Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design program A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the c...	11/22/2011
8060850	Method for designing semiconductor integrated circuit A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurali...	11/15/2011
8055494	Reporting delay in modeling environments Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of the model is determined and reported to users before executing the m...	11/08/2011
8046725	Method of incremental statistical static timing analysis based on timing yield Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual...	10/25/2011
8036873	Efficient clock models and their use in simulation Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used. ...	10/11/2011
8024683	Replicating timing data in static timing analysis operation An apparatus, method and program product create multiple copies of a clock signal, or phase, to analyze timing operations within a single timing run of a static timing analysis operation. At least one path comprising logical user defined delay segments and a timing ...	09/20/2011
8010932	Structure for automated transistor tuning in an integrated circuit design A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit des...	08/30/2011
8000951	Timing analysis method and apparatus for enhancing accuracy of timing analysis and improving work efficiency thereof A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when ...	08/16/2011
7992122	Method of placing and routing for power optimization and timing closure A method, algorithm, software, architecture and/or system for placing circuit blocks and routing signal paths or connections between the circuit blocks in a circuit design is disclosed. In one embodiment, a method of placing and routing can include: (i) routing sign...	08/02/2011
7987440	Method and system for efficient validation of clock skews during hierarchical static timing analysis A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arriva...	07/26/2011
7983891	Receiver dependent selection of a worst-case timing event for static timing analysis A method for determining a worst-case transition is disclosed. The method includes determining a plurality of output slews for the plurality of input signals based on a timing model of a gate and selecting a worst delay input signal from the plurality of input signa...	07/19/2011
7979825	Method and system for the calculation of the sensitivities of an electrical parameter of an integrated circuit A method and system for determining electrical parameter data for a layer of an integrated circuit that can include a nominal electrical parameter value, and sensitivity values which represent the sensitivities of the nominal electrical parameter value to variations...	07/12/2011
7971169	System and method for reducing the generation of inconsequential violations resulting from timing analyses A system for, and method of, reducing the generation of inconsequential violations resulting from timing analyses and an electronic design automation (EDA) tool incorporating the system or the method. In one embodiment, the system includes: (1) a timing violation id...	06/28/2011
7941775	Arbitrary waveform propagation through a logic gate using timing analysis results An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at...	05/10/2011
7933761	Creation of clock and data simulation vectors with periodic jitter Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced a...	04/26/2011
7930668	Placement and routing using inhibited overlap of expanded areas Methods of placing and routing a logic design are provided. The logic design includes logic elements and nets connecting the logic elements. A first placement and a partial routing of the logic elements and the nets of the logic design are generated. The partial rou...	04/19/2011
7904852	Method and system for implementing parallel processing of electronic design automation tools Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may...	03/08/2011
7873506	Simulation framework with support for multiple integrated circuits having potentially differing characteristics The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having poten...	01/18/2011
7860703	Timing control method of hardware-simulating program and application of the same A timing-control method of a hardware-simulating program can be applied to a software platform for facilitating control program development. The hardware-simulating program can be recorded in any suitable recording medium and defines therein a plurality of simulatin...	12/28/2010
7801719	Processor-based system analysis automation In an embodiment, data in a first processor-based system is captured and serialized into an XML format. The XML-formatted data is transmitted to a second processor-based system, it is deserialized into a non-XML format, and it is processed in the second processor-ba...	09/21/2010
7783467	Method for digital system modeling by using higher software simulator A digital system design method uses a higher programming language. In order to realize a digital system, an algorithm is verified based on a program written by the higher programming language and a program is programmed considering the higher programming language-ha...	08/24/2010
7778814	Method and device for simulating an automation system A method and a device for simulating an automation system are disclosed. The aim of the invention is to allow an automation system to be simulated in such a way that simulation components operating at very different computing speeds can be combined into an overall s...	08/17/2010
7761280	Data processing apparatus simulation by generating anticipated timing information for bus data transfers Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over ...	07/20/2010
7747426	System simulation using multi-tasking computer code A system, such as hardware or software system having a number of modules, is simulated using multi-tasking computer code. Simulation computer code launches tasks simulating system execution, where each task corresponds to a module. Each task requests a processing de...	06/29/2010
7739098	System and method for providing distributed static timing analysis with merged results Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time co...	06/15/2010
7739097	Emulation system with time-multiplexed interconnect A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plur...	06/15/2010
7689401	Method of circuit simulation for delay characteristic evaluation, circuit simulation program and circuit simulation device In delay characteristic evaluation of a logical circuit, there was the problem of underestimation of the output load compared with the actual output load. There is provided a simulation device including a simplification section that, simplifies the load circu...	03/30/2010
7647220	Transistor-level timing analysis using embedded simulation A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays usi...	01/12/2010
7542892	Reporting delay in modeling environments Methods and systems for automatically reporting delay incurred in a model is disclosed. The delay may be incurred in a part or in an entire portion of the model. Delay incurred in each component of the model is determined and reported to users before executing the m...	06/02/2009
7496491	Delay calculation method capable of calculating delay time with small margin of error A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that ...	02/24/2009
7487078	Method and system for modeling distributed time invariant systems A reduced order model of a distributed time invariant system is produced by projecting system matrices onto smaller matrices, interpolating the matrices and placing into a state-space system. The system matrices are an internal representation of the distributed time...	02/03/2009

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Class 703/19 - Timing