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| Number | Title | Issue Date |
| 5892938 | Interactive interface system An interactive system for interfacing with signal processing apparatus having a network of interconnected processors (e.g., for a digital audio mixing console) uses a graphical user interface for monitoring the operation of the system. The graphical user ... | 04/06/1999 |
| 5880966 | Apparatus using scoring advisors having outputs combined on a back plane for evaluating designs Apparatus for evaluating a design includes a memory for storing data representing a current design for the device; a host processor connected to the memory and having a change input for receiving an input signal representing a change in the design, an eve... | 03/09/1999 |
| 5850345 | Synchronous distributed simulation apparatus and method The present invention provides a synchronous distributed simulation apparatus having a simulation supervising device which supervises a simulation device, and the simulation device which performs a synchronous simulation under supervision of the simulatio... | 12/15/1998 |
| 5812435 | Shape simulation method allowing simulation of processed shape during steps of manufacturing a semiconductor device in a short period of time An area to which volume ratio "1" as allotted in an analysis area is divided into first and second types of cells. A third cell is placed next to and above the first cell, and volume ratio "0" is allotted to the third cell. With respect to the direction i... | 09/22/1998 |
| 5809283 | Simulator for simulating systems including mixed triggers A method of simulating a system on a computer. The method comprises the following steps. First, analyze a hardware design language specification of the system to identify a set of processes. The hardware design language specification includes a register t... | 09/15/1998 |
| 5798950 | Method and apparatus for estimating durations of activities in forming a current system, based on past durations of activities in forming past systems Durations of activities in forming a system (the "current system") are estimated, using data including i) durations of first activities and scores for a number of previously formed systems (the "past systems"), ii) scores for the current system, and iii) ... | 08/25/1998 |
| 5794005 | Synchronous parallel emulation and discrete event simulation system with self-contained simulation objects and active event objects The present invention is embodied in a method of performing object-oriented simulation and a system having interconnected processor nodes operating in parallel to simulate mutual interactions of a set of discrete simulation objects distributed among the n... | 08/11/1998 |
| 5790829 | Event synchronization mechanism A computer process determines that processing by a resource manager of all previously sent event structures has been completed by sending a tag event structure after having sent the previously sent event structures and waiting for the tag event structure ... | 08/04/1998 |
| 5784592 | Computer system which includes a local expansion bus and a dedicated real-time bus for increased multimedia performance A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. ... | 07/21/1998 |
| 5764953 | Computer implemented system for integrating active and simulated decisionmaking processes A system that integrates active and simulated decisionmaking processes generates decisions in response to events representing changes in a domain model, and updates the domain model according to the decisions. The system includes a real-time mode for gene... | 06/09/1998 |
| 5701439 | Combined discrete-event and continuous model simulation and analysis tool The tool comprises the first step of providing a first software component, serving as a timing element, for receiving global synchronization commands as input and issuing global simulation scheduler task dispatch commands as output. A second software comp... | 12/23/1997 |
| 5696942 | Cycle-based event-driven simulator for hardware designs A method and apparatus for simulation of a hardware design using a cycle-based event-driven simulation. The present invention also provides for a measuring technique for estimating the potential performance gain obtained by using traditional simulation te... | 12/09/1997 |
| 5661662 | Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on th... | 08/26/1997 |
| 5615137 | On-the-fly model checking with partial-order state space reduction An on-the-fly verification system which employs statically-available information to reduce the size of the state space required to verify liveness and safety properties of a target system consisting of asynchronous communicating processes. The verificatio... | 03/25/1997 |
| 5608908 | Process control system responsive to device events Techniques for controlling a process which is performed at least in part by a device such as a computer operating system. The techniques involve a process server which controls the process in response to indications that steps of the process have taken pl... | 03/04/1997 |
| 5574893 | Computer logic simulation with dynamic modeling A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predeterm... | 11/12/1996 |
| 5553008 | Transistor-level timing and simulator and power analyzer A method for accurately simulating the timing and power behavior of digital MOS circuits is provided. The method includes piece-wise linear modeling of transistors, dynamic and static construction of channel connected components, event driven simulation a... | 09/03/1996 |
| 5544348 | Simulation method and apparatus A method and apparatus is provided to simulate a system that is modelled by object frames which describe information on the events to be processed by the system, and a root frame that contains information on the conditions and times of the simulation. The... | 08/06/1996 |
| 5542069 | Method and apparatus for simulating input events in a windowed environment An input device emulator comprises an interpreter and a router is provided to a windowed environment. The interpreter reads and interprets commands of a first application program and generates simulated input device messages. The router routes the simulat... | 07/30/1996 |
| 5537548 | Method of computer conferencing by intercepting commands issued by application programs and redirecting to all stations for execution During execution, API calls to the operating system in a master processor are transferred to slave processors by an event redirection mechanism, the API calls are then provided to the operating systems of the slave processors by their event redirection me... | 07/16/1996 |
| 5467462 | Event driven logic simulator for partial simulation Event driven logic simulator for partial simulation is provided. An event storage has an event attribute storage section for indicating whether an event is preset before the execution of simulation by the operator. The node information storage has an even... | 11/14/1995 |
| 5446676 | Transistor-level timing and power simulator and power analyzer A method for accurately simulating the timing and power behavior of digital MOS circuits is provided. The method includes piece-wise linear modeling of transistors, dynamic and static construction of channel connected components, event driven simulation a... | 08/29/1995 |
| 5426768 | Logic simulation with efficient deadlock avoidance by selectively suspending event data fetch based on element information Disclosed is a method for simulating an operation of an event driven logic circuit in response to changes of the signal status of each terminal of all the elements in the logical circuit, based on event data each containing event time indicating when the ... | 06/20/1995 |
| 5418735 | Detection of event-outstripping and glitches in hardware logic simulator Event packets are input to an event handler both in a scheduling phase and in a dispatching phase of an event scheduler. In the scheduling phase, EVCNT of a device of an occurring event is counted up by 1, and in the dispatching phase, EVCNT of a device o... | 05/23/1995 |
| 5384720 | Logic circuit simulator and logic simulation method having reduced number of simulation events A logic simulation system and method reduces the number of events to be simulated. The simulator receives a user specified circuit netlist denoting a specified logic circuit's components and the nodes interconnecting those components. A user specified wat... | 01/24/1995 |
| 5375074 | Unboundedly parallel simulations Efficient simulation is achieved by employing a highly efficient ordering of the events to be simulated. Specifically, the events to be simulated are grouped into layers and the layers are simulated in order. Each of the layers consists of events that are... | 12/20/1994 |
| 5272651 | Circuit simulation system with wake-up latency An event-driven logic simulator provides for future evaluation events. Evaluation latencies are assigned to respective inputs of components based on component type. At least some of these latencies are positive and finite. When a signal status event speci... | 12/21/1993 |
| 5157620 | Method for simulating a logic system A logic simulator has a time loop with a number of time slots into which events are scheduled. The events are wrapped around the loop, so that event times corresponding to different cycles around the loop may be simultaneously present on the loop. This al... | 10/20/1992 |
| 5081601 | System for combining independently clocked simulators Two or more independently clocked simulators are interconnected in a manner which prevents signal exchange at a time when the internal simulation clocks of the simulators point to different times on a simulated time line. Each simulator transmits to one o... | 01/14/1992 |
| 5068812 | Event-controlled LCC stimulation A method for simulating a levelized logic circuit including an event-controlled feature for marking components to be reevaluated. An evaluation list is formed which lists signals and corresponding components of the logic circuit which are to be reevaluate... | 11/26/1991 |
| 4985860 | Mixed-mode-simulator interface A mixed-mode-simulator interface synchronizes, at non-regular intervals, a system simulator which includes an analog realm and an event-driven realm, wherein both simulators perform a simulation on a single, mixed-mode system. The interface uses an error-... | 01/15/1991 |
| 4967386 | Simulation method for modifiable simulation model A simulation method includes a step of modifying a model in a simulation process, a step of detecting elements influenced by the model modification, and a step of performing a resimulation process while returning to the earliest one of the influenced elem... | 10/30/1990 |
| 4965743 | Discrete event simulation tool for analysis of qualitative models of continuous processing system An artificial intelligence design and qualitative modelling tool is disclosed for creating computer models and simulating therein continuous activities, functions and/or behavior using developed discrete event techniquers. Conveniently, the tool is organi... | 10/23/1990 |
| 4916647 | Hardwired pipeline processor for logic simulation Computer for implementing an event driven algorithm which utilizes a master processor and a plurality of processors arranged in modules, wherein the processors within the module are capable of operating independently of each other. The various modules are... | 04/10/1990 |
| 4901260 | Bounded lag distributed discrete event simulation method and apparatus A discrete event simulation system that avoids all blocking and advances the simulation time in an efficient manner by treating the simulated system as a set of subsystems and simulating the subsystems concurrently. The simulation proceeds iteratively by ... | 02/13/1990 |
| 4873656 | Multiple processor accelerator for logic simulation Computer for implementing an event driven algorithm which utilizes a master processor and a plurality of processors arranged in modules, wherein the processors within the module are capable of operating independently of each other. The various modules are... | 10/10/1989 |
| 4814983 | Digital computer for implementing event driven simulation algorithm A computer for implementing an event driven algorithm which is used in conjunction with a master computer is disclosed. The computer includes a plurality of processors coupled in a ring arrangement each of which is microprogrammable. Each processor includ... | 03/21/1989 |
| 4751637 | Digital computer for implementing event driven simulation algorithm A computer for implementing an event driven algorithm which is used in conjunction with a master computer is disclosed. The computer includes a plurality of processors coupled in a ring arrangement each of which is microprogrammable. Each processor includ... | 06/14/1988 |
