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| Number | Title | Issue Date |
| 6028993 | Timed circuit simulation in hardware using FPGAs A logic circuit is simulated for mapping and emulation on a field programmable gate array-based platform by mapping one or more of the circuit delays onto delay elements in the FPGA-based platform. The operations of the delay elements are controlled by on... | 02/22/2000 |
| 6018624 | Method to back annotate programmable logic device design files based on timing information of a target technology One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simu... | 01/25/2000 |
| 6006027 | Method and apparatus for event simulation A method and apparatus for inserting an event into a simulation time queue, wherein the simulation time queue is represented by a tree structure having a top node which represents the total number of "time slices" to be simulated, intermediate nodes repre... | 12/21/1999 |
| 6002861 | Method for performing simulation using a hardware emulation system A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on th... | 12/14/1999 |
| 5987243 | Hardware and software co-simulator and its method The disclosed hardware and software co-simulator can execute two simulations effectively between two simulators each for executing simulation independently, by eliminating the idle times for waiting the execution end of the opposite simulator. The co-simu... | 11/16/1999 |
| 5960188 | Method for modeling electrical interconnections in a cycle based simulator The present invention relates to a method and apparatus for verifying the correct performance of software on an electrical system by use of a cycle-based simulator. More specifically, it relates to an apparatus and method for simulating an electrical inte... | 09/28/1999 |
| 5956498 | Method of improving store efficiency and memory allocation in code generated by a circuit compiler Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's re... | 09/21/1999 |
| 5946472 | Apparatus and method for performing behavioral modeling in hardware emulation and simulation environments In accordance with the present invention, a system for providing high-speed sequential modeling in a simulator or emulator environment is provided. The system includes a sequential control system (microprocessor board) which is attached directly to an emu... | 08/31/1999 |
| 5943489 | Logic simulation system for logic simulation of the semiconductor integrated circuit A logic simulation system which comprises a connection data conversion section to convert the format of the connection data, a dump data generation section to generate and output the dump data, a data pattern generation section to generate and output the ... | 08/24/1999 |
| 5937179 | Integrated circuit design system with shared hardware accelerator and processes of designing integrated circuits An interactive environment is provided for integrated circuit (IC) designers to do an emulation session on a hardware accelerator 111 and then move to simulator 131, and vice versa. An aspect of the present inventive solution swaps memory state and logic ... | 08/10/1999 |
| 5931963 | Fault simulation apparatus A fault simulation apparatus includes an MOS transistor output signal strength determining portion for extracting the conductivity type of an MOS transistor in which an event such as a variation in signal level occurs. A control signal value is obtained f... | 08/03/1999 |
| 5920485 | Method of selecting gates for efficient code generation by a circuit compiler Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's re... | 07/06/1999 |
| 5903475 | System simulation for testing integrated circuit models Systems and methods of verifying the design of the ASIC during design and implementation phases are provided. The ASIC design is verified utilizing information from a system simulation in the customer's system environment. During system simulation, the in... | 05/11/1999 |
| 5903468 | Determining maximum load index for tabular timing models In accordance with the preferred embodiment of the present invention, a logic cell library is built. Within the logic cell library a timing model for a first logic cell is generated. In order to generate the timing model a number of indices which specify ... | 05/11/1999 |
| 5903580 | Fault simulator of creating a signal pattern for use in a fault inspection of a semiconductor integrated circuit A fault simulator comprises a storage for storing a truth table that is a fault model, a simulation executing unit for executing a simulation on the basis of a given signal pattern by the use of the truth table stored in the storage, a simulation result j... | 05/11/1999 |
| 5901061 | Method of checking for races in a digital design A method of using a fet level simulator to check for races in a digital design. The method comprises varying digital design models input into the simulator. Each model comprises a clock gater circuit producing clocks with differing overlaps and dead times... | 05/04/1999 |
| 5901305 | Simulation method and apparatus for semiconductor integrated circuit The invention provides a simulation method and apparatus for a semiconductor integrated circuit which can perform simulation of an operation characteristic of each of a plurality of circuit blocks of a semiconductor integrated circuit and simulation of si... | 05/04/1999 |
| 5896401 | Fault simulator for digital circuitry A fault simulator for a digital combinational circuit implements a critical path tracing algorithm in reconfigurable hardware and comprises: a forward network capable of emulating the digital combinational circuit and having primary outputs; a second forw... | 04/20/1999 |
| 5892940 | Aliasing nodes to improve the code generated by a circuit compiler Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's re... | 04/06/1999 |
| 5889954 | Network manager providing advanced interconnection capability A network manager for configuring and controlling a simulated telecommunications network having a plurality of nodes which communicate in a plurality of communications protocols. The network manager dynamically connects and disconnects each of the plurali... | 03/30/1999 |
| 5889685 | Method and apparatus for automatically characterizing short circuit current and power consumption in a digital circuit Short-circuit current and power consumption for an integrated circuit may be calculated by measuring short-circuit current for various cells within an integrated circuit using a Verilog™ logic level model of the cell. Each cell within an integrated circ... | 03/30/1999 |
| 5872953 | Simulating circuit design on a circuit emulation system A circuit transformation software module incorporating the teachings of the present invention is provided to an otherwise conventional emulation system. The circuit transformation software module takes a circuit design as input and transforms it into a "n... | 02/16/1999 |
| 5862361 | Sliced synchronous simulation engine for high speed simulation of integrated circuit behavior A custom simulation engine is provided which operates upon a set of statically scheduled events. The simulation engine is automatically created from a functional description of the integrated circuit design. Each element of each partition within the funct... | 01/19/1999 |
| 5856933 | System and method for digital simulation of an electrical circuit A system for digital simulation of an electric circuit is disclosed. The system is event-driven, and functions on a gate inversion principle, to simulate an electric circuit. According to the gate inversion principle, any gates or gate arrangements in the... | 01/05/1999 |
| 5822567 | Method of and apparatus for simulating integrated circuit A simulator speedily simulates an integrated circuit. The simulator has a digital simulator for simulating a digital part of the integrated circuit in each of sections divided from a total simulation time, an analog simulator for simulating an analog part... | 10/13/1998 |
| 5818736 | System and method for simulating signal flow through a logic block pattern of a real time process control system A testing system for, and method of, simulating signal flow through a logic block pattern of a real time process control system. The system includes: (1) a memory that contains a data base of input data associated with simulated sensors and a rule base co... | 10/06/1998 |
| 5812431 | Method and apparatus for a simplified system simulation description A method and apparatus simulates the performance of a system from a user-specified description of the components in the system and the interconnections between the components. The user may specify the descriptions using a consistent syntax. Conservation r... | 09/22/1998 |
| 5809283 | Simulator for simulating systems including mixed triggers A method of simulating a system on a computer. The method comprises the following steps. First, analyze a hardware design language specification of the system to identify a set of processes. The hardware design language specification includes a register t... | 09/15/1998 |
| 5805859 | Digital simulator circuit modifier, network, and method Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent o... | 09/08/1998 |
| 5796990 | Hierarchical fault modeling system and method A system and method for generating a fault model for a logic circuit includes a data storage device for storing information relative to fault models or primitive elements in a logic circuit and for storing fault models for each level of design in a hierar... | 08/18/1998 |
| 5768160 | Logical simulator with event load measuring and model recreating units for parallel processing elements A logical simulator that creates a logical simulation model that can equally distribute the load to each processing element and certainly suppress a decrease in a parallel processing efficiency due to each processing element waiting for its synchronous op... | 06/16/1998 |
| 5650947 | Logic simulation method and logic simulator A method is disclosed to execute an event driven logic simulation to check the function of a logic circuit, by using a logic simulator. The logic simulator includes at least one data base and a processing unit having a dummy element synthesizer. The dummy... | 07/22/1997 |
| 5650946 | Logic simulator which can maintain, store and use historical event records A system and method for event-driven simulation of a circuit is disclosed. The system includes a simulation history of events and node values at various times throughout the simulation of the circuit. The system allows the user to access the simulation hi... | 07/22/1997 |
| 5649164 | Sets and holds in virtual time logic simulation for parallel processors In an event-driven, virtual time logic simulation system, user-initiated requests for setting and holding simulated logic circuit elements are accommodated during forward simulation, rollback, and advance of system global virtual time.... | 07/15/1997 |
| 5592655 | Logic simulation method For simulation evaluation of combinational logic, changes in input signals are reserved for events occurring with respect to every element of the combinational logic circuit or of a partial circuit within the logic circuit according to demand timing. To i... | 01/07/1997 |
| 5467462 | Event driven logic simulator for partial simulation Event driven logic simulator for partial simulation is provided. An event storage has an event attribute storage section for indicating whether an event is preset before the execution of simulation by the operator. The node information storage has an even... | 11/14/1995 |
| 5467292 | Logical operation method employing parallel arithmetic unit A logical operation method for evaluating a train of output data to be obtained when a plurality of input patterns are successively applied to a memory element whose output value depends upon a sequence of input values. For each of the plurality of patter... | 11/14/1995 |
| 5426768 | Logic simulation with efficient deadlock avoidance by selectively suspending event data fetch based on element information Disclosed is a method for simulating an operation of an event driven logic circuit in response to changes of the signal status of each terminal of all the elements in the logical circuit, based on event data each containing event time indicating when the ... | 06/20/1995 |
| 5418735 | Detection of event-outstripping and glitches in hardware logic simulator Event packets are input to an event handler both in a scheduling phase and in a dispatching phase of an event scheduler. In the scheduling phase, EVCNT of a device of an occurring event is counted up by 1, and in the dispatching phase, EVCNT of a device o... | 05/23/1995 |
| 5410673 | Method and apparatus for simulating a logic circuit having a plurality of interconnect logic blocks A computer program-implemented logic circuit simulation receives data describing the configuration of a logic circuit to be simulated, and a library of component characteristics incorporated in the circuit. Signals are classified as a first type always to... | 04/25/1995 |
