Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 8191024 | Customizable H-tree synthesis tool A computer program for generating an H-tree for an integrated circuit design stored on a computer readable medium includes code to receive from a user a set of parameters to configure the H-tree. The parameters include a starting segment length and an ending segment... | 05/29/2012 |
| 8191033 | In situ clock jitter measurement Embodiments of the present invention provide a method/apparatus to measure the jitter of a timing signal used in an integrated circuit chip. The method/apparatus is used to send data from a launch element using a synchronous data path of the timing signal, receive t... | 05/29/2012 |
| 8185854 | Method and apparatus for performing parallel slack computation within a shared netlist region A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed. | 05/22/2012 |
| 8185853 | Transforming variable domains for linear circuit analysis Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, dom... | 05/22/2012 |
| 8181134 | Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under w... | 05/15/2012 |
| 8176452 | Method and apparatus for circuit partitioning and trace assignment in circuit design Methods and apparatuses for incremental circuit partitioning and incremental trace assignment. In one embodiment of the present invention, a cost function based on both the partitioning solution and the trace assignment solution is used for the partitioning of a cir... | 05/08/2012 |
| 8176451 | Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acqui... | 05/08/2012 |
| 8171438 | Verification of a program partitioned according to the control flow information of the program Provided are a method, system, and article of manufacture for verification of a program partitioned according to the control flow information of the program. Properties are received indicating outcome states for a program. The program is processed to determine a con... | 05/01/2012 |
| 8171440 | Timing analyzing apparatus, timing analyzing method and program thereof A timing analyzing apparatus according to an exemplary aspect of the invention includes, a storage apparatus which stores a global clock list including information on clock paths inside and outside a partial area of an electronic circuit, and a post layout processin... | 05/01/2012 |
| 8166431 | Reducing startup time of an embedded system that includes an integrated circuit A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsi... | 04/24/2012 |
| 8160860 | Method and apparatus for event-based simulation of a digital design having a power shut-off feature Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power sta... | 04/17/2012 |
| 8156456 | Unified design methodology for multi-die integrated circuits A method of designing an integrated circuit (IC) having multiple dies can include identifying a unified design library having a first process node specific (PNS) library for a first IC process technology and a second PNS library for a second IC process technology. T... | 04/10/2012 |
| 8141013 | Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device... | 03/20/2012 |
| 8140316 | Systems and methods for improving digital system simulation speed by clock phase gating An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simu... | 03/20/2012 |
| 8136063 | Unfolding algorithm in multirate system folding Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit opera... | 03/13/2012 |
| 8132140 | Analyzing device for circuit device, circuit device analyzing method, analyzing program, and electronic medium A circuit board analyzing method and a circuit board analyzer are provided which can greatly reduce analyzing time. The circuit board analyzer includes a computing unit 110, a memory unit 140 connected to the computing unit 110, and an input uni... | 03/06/2012 |
| 8112265 | Simulating loss of logic power state due to processor power conservation state In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific... | 02/07/2012 |
| 8108815 | Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantiz... | 01/31/2012 |
| 8108816 | Device history based delay variation adjustment during static timing analysis A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a... | 01/31/2012 |
| 8108819 | Object placement in integrated circuit design A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for int... | 01/31/2012 |
| 8091051 | Behavioral synthesis apparatus, method, and program having test bench generation function Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation mea... | 01/03/2012 |
| 8082527 | Representing the behaviors of a packet processor Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative d... | 12/20/2011 |
| 8079004 | Efficient exhaustive path-based static timing analysis using a fast estimation technique One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more... | 12/13/2011 |
| 8074192 | Verification support apparatus, verification support method, and computer product The circuit volume of a system under design is reduced by a circuit conversion involving consolidation (sharing) of common parts in the system by a representative part. The design data of the system post-conversion is used to verify operation of the system. However,... | 12/06/2011 |
| 8050904 | System and method for circuit symbolic timing analysis of circuit designs A method, data processing system, and computer program product are provided for performing time-based symbolic simulation. A delay-aware representation of a circuit is created that includes a plurality of circuit nodes. The data-aware representation is simulated. In... | 11/01/2011 |
| 8042085 | Method for compaction of timing exception paths A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design opti... | 10/18/2011 |
| 8037438 | Techniques for parallel buffer insertion The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence... | 10/11/2011 |
| 8028259 | Automated method and apparatus for very early validation of chip power distribution networks in semiconductor chip designs Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid d... | 09/27/2011 |
| 8020123 | Transaction-based system and method for abstraction of hardware designs Apparatus and method for transaction-based abstraction process can, in an embodiment, include three main phases: first, selecting a set of transaction-processing finite state machines (FSMs) that determine transaction boundaries. Second, extracting the transaction-p... | 09/13/2011 |
| 8020129 | Multiple voltage threshold timing analysis for a digital integrated circuit An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digita... | 09/13/2011 |
| 8010921 | System and method for statistical timing analysis of digital circuits The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random... | 08/30/2011 |
| 7987086 | Software entity for the creation of a hybrid cycle simulation model Disclosed is a software entity for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs,... | 07/26/2011 |
| 7979819 | Minterm tracing and reporting Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more ... | 07/12/2011 |
| 7975249 | Operation timing verifying apparatus and program An operation timing verifying apparatus and program for accurately verifying operation timings of a semiconductor integrated circuit in design with suppressing design time and cost. The operation timing verifying apparatus and program sets an unreal corner condition... | 07/05/2011 |
| 7971166 | Method, system, and program product for automated verification of gating logic using formal verification Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testb... | 06/28/2011 |
| 7962874 | Method and system for evaluating timing in an integrated circuit Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and lat... | 06/14/2011 |
| 7949510 | Distributed simultaneous simulation A method and system for distributed simultaneous simulation are provided, the method including providing a state of at least one storage unit, providing a segment of the circuit bounded by the at least one storage unit, and simulating the segment in accordance with ... | 05/24/2011 |
| 7941774 | Partial timing modeling for gate level simulation Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a ... | 05/10/2011 |
| 7934190 | Multiple amplifier matching over lumped networks of arbitrary topology A method includes generating at least one matrix representing a two-port, generating gain, noise, and stability functions of a system comprising the two-port, a generator connected to one port of the two-port, the generator having a generator reflectance, and a load... | 04/26/2011 |
| 7930662 | Methods for automatically generating fault mitigation strategies for electronic system designs Approaches for generating a design of an electronic system are disclosed. In one approach, for each of one or more components of a first specification of the design, an error mitigation technique is selected from among multiple different error mitigation techniques ... | 04/19/2011 |
