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| Number | Title | Issue Date |
| 6985843 | Cell modeling in the design of an integrated circuit The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/o... | 01/10/2006 |
| 6986114 | Feedback cycle detection across non-scan memory elements All feedback cycles in a circuit network which cross only non-scannable memory elements are detected in linear run time. The method models a circuit network as a directed graph, then attributes network elements so that a single feedback cycle may be found in constan... | 01/10/2006 |
| 6983427 | Generating a logic design A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includ... | 01/03/2006 |
| 6980941 | Method and computer program product for realizing a system specification which is described in a system description language A system design support system is disclosed, which handles specifications at system level, e.g., a specification of software executed by a computer, specification of hardware implemented by combining semiconductor devices and the like, a specification of an incorpor... | 12/27/2005 |
| 6978216 | Testing of integrated circuits from design documentation One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an integrated circuit design simulator software, a storage media, a storage device, user interface, and a d... | 12/20/2005 |
| 6978214 | Validation of electrical performance of an electronic package prior to fabrication An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of... | 12/20/2005 |
| 6975972 | Dynamic association of equations to unknowns during simulations of systems described by hardware description languages In simulating a physical circuit or system including analog and mixed signal digital-analog components, a computer models the physical circuit or system as a system of simultaneous equations. Conditional equations with associated conditions that can be true or false... | 12/13/2005 |
| 6975978 | Method and apparatus for fault simulation of semiconductor integrated circuit A test pattern sequence is generated (101), then a logic simulation of the operation of an IC under test in the case of applying each test pattern of the test pattern sequence, and a logic signal value sequence occurring in each signal line of the IC under te... | 12/13/2005 |
| 6975976 | Property specific testbench generation framework for circuit design validation by guided simulation Simulation continues to be the primary technique for functional validation of designs. It is important that simulation vectors be effective in targeting the types of bugs designers expect to find rather than some generic coverage metrics. The focus of this work is t... | 12/13/2005 |
| 6973417 | Method and system for simulating execution of a target program in a simulated target system A method and system for simulating the execution of a software program on a simulated hardware system. An instrumented software program is divided into program segments delineated by tags and is then analyzed for data describing the program segments. The data is tab... | 12/06/2005 |
| 6973422 | Method and apparatus for modeling and circuits with asynchronous behavior A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element. ... | 12/06/2005 |
| 6970813 | Insight architecture visualization tool A system and method that facilitates the modeling of an architecture through XML configuration is presented. Using this system and method, system developers that are developing a modeled architecture may, before system implementation begins, visualize and understand... | 11/29/2005 |
| 6970814 | Remote IP simulation modeling A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wid... | 11/29/2005 |
| 6971074 | Layout device A layout device includes a processing type setting part for classifying a layout of a semiconductor integrated circuit in every area in accordance with the percentage voltage drop in the circuit, and for extracting a processing target portion composed of a group of ... | 11/29/2005 |
| 6970815 | Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data ca... | 11/29/2005 |
| 6971084 | System and method for synchronizing execution of a batch of threads A method for creating a computer program to be executed by a plurality of threads, in which the method utilizes a technique for execution synchronization referred to herein as a batch synchronization section. According to this technique, a plurality of threads may b... | 11/29/2005 |
| 6968305 | Circuit-level memory and combinational block modeling A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup tab... | 11/22/2005 |
| 6968525 | Implementing method for buffering devices An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the pr... | 11/22/2005 |
| 6968520 | System verifying apparatus and method which compares simulation result based on a random test program and a function simulation An apparatus and method which verify a system including a microprocessor. The apparatus includes first and second simulators which verify a target architecture using a test program and a functional description of the system, respectively. The first and second simlat... | 11/22/2005 |
| 6968285 | Method and apparatus for scenario search based random generation of functional test suites A method of describing a set of tests capable of being performed on a device under test (DUT) is disclosed. The method includes identifying a scenario space of the DUT. ... | 11/22/2005 |
| 6965852 | Pseudo random test pattern generation using Markov chains A driver module is provided that generates test patterns with desired tendencies. The driver module provides these test patterns to controlling code for simulation of a hardware model. The test patterns are generated by creating and connecting subgraphs in a Markov ... | 11/15/2005 |
| 6965853 | Back annotation apparatus for carrying out a simulation based on the extraction result in regard to parasitic elements A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verificat... | 11/15/2005 |
| 6964027 | System and method for optimizing exceptions A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redunda... | 11/08/2005 |
| 6961690 | Behaviorial digital simulation using hybrid control and data flow representations The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of controlling the simulation of a digital circuit in such a way that desi... | 11/01/2005 |
| 6959271 | Method of identifying an accurate model A method is described for identifying an inaccurate model of a hardware circuit. The method includes the steps of simulating the model of the circuit by applying a plurality of signals, said plurality of signals having at least one abstract data type level to provid... | 10/25/2005 |
| 6959257 | Apparatus and method to test high speed devices with a low speed tester An apparatus coupled to a low speed tester and a device is disclosed. The device may have a first speed faster than a second speed of the low speed tester. The apparatus may be configured to allow the low speed tester to perform high speed tests of the device at the... | 10/25/2005 |
| 6957178 | Incremental automata verification Methods and apparatus for performing formal verification of a system defined by a set of automata are useful in facilitating computing efficiencies during the verification of an incremental system design. The various embodiments permit computing efficiencies by savi... | 10/18/2005 |
| 6957413 | System and method for specifying integrated circuit probe locations A method for including probe locations in an integrated circuit may include specifying probe cells prior to the place and route stage of the design process. The probe cell locations may be specified in a functional description of the integrated circuit, such as an H... | 10/18/2005 |
| 6947882 | Regionally time multiplexed emulation system A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are recon... | 09/20/2005 |
| 6947883 | Method for designing mixed signal integrated circuits and configurable synchronous digital noise emulator circuit A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of gates equivalent to a number of gates in the digital circuit portion, aff... | 09/20/2005 |
| 6948145 | Tool suite for the rapid development of advanced standard cell libraries employing the connection properties of nets to identify potential pin placements A library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs. The tool suite may include a post operations tool, an audit tool, a custom inter... | 09/20/2005 |
| 6944552 | System and method for detecting power deficiencies in a computer component One embodiment of the invention is a method for analyzing power in a component comprising determining a plurality of current densities, wherein each current density is associated with one portion of a plurality of portions of the component, determining a plurality o... | 09/13/2005 |
| 6944837 | System and method for evaluating an integrated circuit design A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT... | 09/13/2005 |
| 6944582 | Methods for reducing bitline voltage offsets in memory devices A method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bit... | 09/13/2005 |
| 6944584 | System and method for control and simulation A system that controls devices and integrally simulates the controlled motion of devices. The control and simulation system allows simultaneous development hardware and software in controlled device installations and increase operational ease-of-use and diagnostic c... | 09/13/2005 |
| 6941258 | Method, apparatus and computer program product for determination of noise in mixed signal systems A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with the substrate, wherein each gate is configured to perform a switching event. Output of a transistor-level m... | 09/06/2005 |
| 6941256 | Bus structure, database and method of designing interface With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered... | 09/06/2005 |
| 6941257 | Hierarchical processing of simulation model events A method, system, and data structure for instrumenting a cross-hierarchical simulation event are disclosed herein. The cross-hierarchical simulation event is a function of a first simulation event residing at a first level of simulation model hierarchy and a second ... | 09/06/2005 |
| 6941499 | Method to verify the performance of BIST circuitry for testing embedded memory A new method and apparatus to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device is achieved. A set of faults is introduced into an embedded memory behavior model. The embedded memory behavior model com... | 09/06/2005 |
| 6937970 | Multichannel synchronized communication A method is provided of transferring data from a sender process to a plurality of receiver processes in a hardware description language, which uses a language construct which effects synchronised communication between the sender process and the receiver processes. | 08/30/2005 |
