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| Number | Title | Issue Date |
| 8160859 | Medium storing logic simulation program, logic simulation apparatus, and logic simulation method A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first cir... | 04/17/2012 |
| 8146027 | Creating interfaces for importation of modules into a circuit design A computer-implemented method of incorporating a module within a circuit design can include, responsive to identifying the module to be imported into the circuit design, automatically identifying each port of the module, displaying a list of the ports of the module,... | 03/27/2012 |
| 8145467 | Method and apparatus for profiling a hardware/software embedded system Method and apparatus for profiling a hardware/software embedded system are described. In one example, a hardware co-simulation interface is generated between a programmable logic device (PLD) configured with the embedded system and a computer based on a plurality of... | 03/27/2012 |
| 8108195 | Satisfiability (SAT) based bounded model checkers A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, w... | 01/31/2012 |
| 8108810 | Synchronous circuit synthesis using an asynchronous specification A method for specifying and synthesizing a synchronous digital circuit by first accepting a specification of an asynchronous system in which stored values are updated according to a set of state transition rules. For instance, the state transition rules are specifie... | 01/31/2012 |
| 8069026 | Clock gating analyzing apparatus, clock gating analyzing method, and computer product Clock gating analysis of a target circuit having a plurality of clock gates, involves the calculation of a clock gate function for each of the clock gates. The clock gate functions indicate an activation state of the clock gates and a combination of output values fr... | 11/29/2011 |
| 8050903 | Apparatus and method for checkpointing simulation data in a simulator Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a ... | 11/01/2011 |
| 8015517 | Library sizing A cell library is automatically designed. An emphasis of a design methodology is on automatic determination of the desired or needed cell sizes and variants. This method exploits different variants on drive strengths, P/N ratios, topology variants, internal bufferin... | 09/06/2011 |
| 8000950 | Random initialization of latches in an integrated circuit design for simulation Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random ord... | 08/16/2011 |
| 7991605 | Method and apparatus for translating a verification process having recursion for implementation in a logic emulator Method and apparatus for translating a verification process having recursion for implementation in a logic emulator are described. Examples of the invention relate to a method, apparatus, and computer readable medium for translating a verification process for implem... | 08/02/2011 |
| 7983890 | Method and apparatus performing automatic mapping for a multi-processor system A method, apparatus and computer program product for mapping and executing an application on a multi-processor system is presented. At least one array to be considered for distribution among processors of said multi-processor system is indicated. The application is ... | 07/19/2011 |
| 7934179 | Systems and methods for logic verification Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT. ... | 04/26/2011 |
| 7899660 | Technique for digital circuit functionality recognition for circuit characterization A method and system of digital circuit functionality recognition for circuit characterization is disclosed. In one embodiment, a method for determining the valid arcs includes receiving a truth table including state information associated with input pins and their a... | 03/01/2011 |
| 7895029 | System and method of automating the addition of RTL based critical timing path counters to verify critical path coverage of post-silicon software validation tools A system and method for modifying a simulation model and optimizing an application program to produce valid hardware-identified operating conditions that are matched with simulator-identified operating conditions in order to modify a simulator accordingly is present... | 02/22/2011 |
| 7895028 | Structure for increasing fuse programming yield A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string.... | 02/22/2011 |
| 7885801 | Modeling asynchronous behavior from primary inputs and latches Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, ... | 02/08/2011 |
| 7865348 | Performance of circuit simulation with multiple combinations of input stimuli This invention provides techniques and tools for reducing circuit simulation time when an electronic circuit with multiple input vectors is simulated. Instead of running the simulation for each input vector one at a time, the circuit-simulation application runs the ... | 01/04/2011 |
| 7856346 | Emulating multiple bus used within a data processing system A test system for data processing circuit design emulates multiple bus masters and provides an arbitration mechanism for coordinating arbitration between those bus masters in the design emulation. The shared bus being tested may be a multi-layer bus and one or more ... | 12/21/2010 |
| 7835898 | Satisfiability (SAT) based bounded model checkers A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, w... | 11/16/2010 |
| 7835899 | Sequential logic in simulation instrumentation of an electronic system According to a method of simulation processing, a collection of files including one or more HDL source files describing design entities collectively representing a digital design to be simulated is received. The HDL source file(s) include a statement specifying incl... | 11/16/2010 |
| 7809543 | Method, apparatus and computer program product for electrical package modeling A method, apparatus, and computer program product for creating a model representing an electrical network residing in an integrated circuit package. ... | 10/05/2010 |
| 7809544 | Methods of detecting unwanted logic in designs for programmable logic devices Methods of detecting unwanted logic in a configuration bitstream for a programmable logic device (PLD). The bitstream can be reversed engineered to generate a model of the design. The model is then tested for unwanted logic, e.g., logic inserted for the purpose of m... | 10/05/2010 |
| 7778813 | Video coding quantization Modify H.263-type quantization with an adaptive quantization parameter floor; this limits clipping of quantized DCT coefficients and consequent artifacts. The maximum absolute level of AC coefficients of a DCT transformed macroblock provides a minimum quantization p... | 08/17/2010 |
| 7720664 | Method of generating simulation model while circuit information is omitted For the purpose of providing a simulation model allowing gate simulation but is capable of keeping the circuit information on the functional block (IP) secret, a method of generating a simulation model provided herein by the present invention comprises a step of gen... | 05/18/2010 |
| 7643981 | Pulse waveform timing in EinsTLT templates The present invention provides for simulating signal transitions. Circuit characteristics are generated. Circuit characteristics are loaded into memory. Circuit behaviour is simulated. A non-leading edge circuit transition is captured. This occurs in software. ... | 01/05/2010 |
| 7636654 | Differential amplifier and method for generating computer simulation model thereof A differential amplifier and a method for generating a computer simulation model thereof are disclosed. The device is thermally stable through adoption of a ballast resistor to a differential structure of a unit transistor pair, such that the differential amplifier ... | 12/22/2009 |
| 7596483 | Determining timing of integrated circuits The present invention is directed to determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths. Predictions are formed for timing delays in said signal paths in the integrated... | 09/29/2009 |
| 7587305 | Transistor level verilog A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf ce... | 09/08/2009 |
| 7558722 | Debug method for mismatches occurring during the simulation of scan patterns A method and system are disclosed for testing for double shift errors in at least one scan chain of flip-flops during a simulation of the design of a digital integrated circuit chip. At the start of the simulation, outputs of each flip-flop in the scan chain are ini... | 07/07/2009 |
| 7536289 | Method of configuring information processing system and semiconductor integrated circuit A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level an... | 05/19/2009 |
| 7533011 | Simulating and verifying signal glitching A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimul... | 05/12/2009 |
| 7478029 | Cable simulation device and method A cable simulator that comprises an input device configured to receive a communication signal. The cable simulator further comprises a circuit configured to simulate attenuation in both the differential mode and common mode components of a communication signal. ... | 01/13/2009 |
| 7464015 | Method and apparatus for supporting verification, and computer product In a verification supporting apparatus, when an obtaining unit obtains a verification scenario, a substituting unit substitutes an undefined value for a variable value in the verification scenario. A first executing unit executes a logic simulation using an input pa... | 12/09/2008 |
| 7447620 | Modeling asynchronous behavior from primary inputs and latches Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, ... | 11/04/2008 |
| 7444574 | Stimulus extraction and sequence generation for an electric device under test A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block ... | 10/28/2008 |
| 7444276 | Hardware acceleration system for logic simulation using shift register as local cache A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. E... | 10/28/2008 |
| 7433808 | Event-based temporal logic In an embodiment, a computer-implemented method for modeling a system using a finite state machine representation is presented. An event-driven temporal logic operator may be associated with a first, active state in the finite state machine representation. A value o... | 10/07/2008 |
| 7433812 | Block diagram modeling A modeling process includes providing blocks, each of the blocks representing functional entities that operate on input signal values, output signal values from the blocks, grouping the output signal values as an ordered set in a multiplexer as a first composite sig... | 10/07/2008 |
| 7430502 | Using thermal management register to simulate processor performance states Systems, methodologies, media, and other embodiments associated with simulating a processor performance state by controlling a thermal management signal are described. One exemplary system embodiment includes a data structure for storing bit patterns that facilitate... | 09/30/2008 |
| 7428484 | Apparatus and method for modeling and analyzing network simulation for network simulation package Provided are an apparatus and method for modeling and analyzing a network simulation for a salable simulation framework (SSF)-based network simulation package. A system logic set is generated and a network simulation modeling suitable for a predetermined network app... | 09/23/2008 |
