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| Number | Title | Issue Date |
| 7366990 | Method and system for managing user activities and information using a customized computer interface Methods and systems for managing user information using a customized computer interface which is user centric and geared toward creating and managing a personal information portal. In one aspect, the invention provides computerized methods for organizing a represent... | 04/29/2008 |
| 7367001 | Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intend... | 04/29/2008 |
| 7366871 | Apparatus and method for determining stack distance including spatial locality of running software for estimating cache miss rates based upon contents of a hash table A method for determining a stack distance including spatial locality for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a merge function on each addre... | 04/29/2008 |
| 7367005 | Method and apparatus for designing a layout, and computer product An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on corr... | 04/29/2008 |
| 7366649 | Method for generating and evaluating a table model for circuit simulation A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions. The method includes the s... | 04/29/2008 |
| 7366650 | Software and hardware simulation A verification environment is provided that co-verifies a software component 8 and a hardware component 10. Within the same environment using a common test controller 18 both hardware stimuli and software stimuli may be applied to their respecti... | 04/29/2008 |
| 7366648 | Electronic circuit analyzing apparatus, electronic circuit analyzing method, and electronic circuit analyzing program The present invention provides an electronic circuit analyzing apparatus for evaluating the reliability value of an analysis result, an electronic circuit analyzing method, and an electronic circuit analyzing program. The electronic circuit analyzing apparatus compr... | 04/29/2008 |
| 7366647 | Bus performance evaluation method for algorithm description The LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation program structuring process and a bus performance evalu... | 04/29/2008 |
| 7366651 | Co-simulation interface Method and apparatus for interfacing between a high-level modeling system and a hardware description language (HDL) co-simulation engine. A plurality of HDL co-simulation engine libraries are queried as to the capabilities of the engines. A co-simulation engine is s... | 04/29/2008 |
| 7363033 | Method of and system for testing equipment during manufacturing A platform system for a mobile terminal for a wireless telecommunications system includes a mobile-terminal platform assembly. The mobile-terminal platform assembly includes a software services component having at least one functional software unit, a hardware compo... | 04/22/2008 |
| 7363097 | Automatic design apparatus, automatic design method, and automatic design program of digital circuit An automatic digital-circuit design apparatus receives a control target model written in a design description language, generates a control target model represented by a finite state machine model, stores the generated control target model, receives a control specif... | 04/22/2008 |
| 7363600 | Method of simulating bidirectional signals in a modeling system A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with ... | 04/22/2008 |
| 7363597 | System for placing elements of semiconductor integrated circuit, method of placing elements thereon, and program for placing elements An element placement system including a placement and routing library that stores element information about logical elements to be placed, placement information containing region information of regions in which logical elements can be placed, and routing information... | 04/22/2008 |
| 7363601 | Integrated circuit selective scaling Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing s... | 04/22/2008 |
| 7363602 | Computer-supported, automated method for the verification of analog circuits The invention relates to a computer-supported, automated method for the verification of analog circuits, and to a storage medium on which a computer software program is stored for performing such method, including transforming of constants or variables characterizin... | 04/22/2008 |
| 7363603 | Method and system for case-splitting on nodes in a symbolic simulation framework A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variabl... | 04/22/2008 |
| 7359813 | Outlier screening technique Multiple parameters of manufactured units are continually measured until some of the units fail, where failure can be accelerated by adjusting operating conditions. Pre-failure data is then examined to find outliers or aberrant parameter values that may have contrib... | 04/15/2008 |
| 7359847 | Tracking converage results in a batch simulation farm network A method and system for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation ... | 04/15/2008 |
| 7360197 | Methods for producing equivalent logic designs for FPGAs and structured ASIC devices An FPGA equivalent of a structured ASIC implementation of a user's logic design is produced by taking advantage of various aspects of the way in which the structured ASIC implementation was produced. For example, the structured ASIC breaks the user's logic design do... | 04/15/2008 |
| 7359911 | System and method for building a database defining a plurality of communication interfaces A system and method for providing seamless communication with threads executing on an embedded computer. Using a DAT system, a programmer can test the communication interfaces of a thread via either a scripting program, any COM-compliant program, or a graphical test... | 04/15/2008 |
| 7360187 | Mixed mode verifier A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines t... | 04/15/2008 |
| 7360193 | Method for circuit block placement and circuit block arrangement based on switching activity A method, algorithm, software, architecture and/or system for placing circuit blocks and/or routing wires in a circuit design is disclosed. In one embodiment, a method of placing can include: (i) determining a first signal path between first and second circuit block... | 04/15/2008 |
| 7360184 | Method and apparatus for scenario search based random generation of functional test suites A method of describing a set of tests capable of being performed on a device under test (DUT) is disclosed. The method includes identifying a scenario space of the DUT. ... | 04/15/2008 |
| 7360186 | Invariant checking In one embodiment, a method for invariant checking includes executing one or more first steps of a finite state machine (FSM) corresponding to one or more binary decision diagrams (BDDs) to traverse a state space of the FSM in a first direction with respect to an in... | 04/15/2008 |
| 7356781 | Method for modifying design data for the production of a component and corresponding units A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are asc... | 04/08/2008 |
| 7356784 | Integrated synthesis placement and routing for integrated circuits A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layo... | 04/08/2008 |
| 7356455 | Optimized interface for simulation and visualization data transfer between an emulation system and a simulator An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buff... | 04/08/2008 |
| 7356424 | Diagnostic compiler for pipeline analog-to-digital converter, method of compiling and test system employing the same The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determi... | 04/08/2008 |
| 7355419 | Enhanced signal observability for circuit analysis Methods and arrangements to enhance photon emissions responsive to a signal within an integrated circuit (IC) for observability of signal states utilizing, e.g., picosecond imaging circuit analysis (PICA), are disclosed. Embodiments attach a beacon to the signal of ... | 04/08/2008 |
| 7353157 | Circuit simulation A system, method, and apparatus select state variables for, build state equations of, and simulate time-domain operation of an electronic circuit. The circuit is modeled with three branch types (inductor, resistor, voltage source in series; capacitor, resistor, curr... | 04/01/2008 |
| 7353158 | Inter integrated circuit extension via shadow memory Embodiments of the present invention include a system for accessing a memory device comprising a master device coupled to a first serial bus. The system further comprises a slave device coupled to a second serial bus wherein the slave device comprises a first memory... | 04/01/2008 |
| 7353161 | System and method for simulating network connection characteristics A system and method for simulating network connection characteristics by alteration of a network packet. In general, the method of the invention includes providing a driver that is capable of accessing all outgoing and incoming network packets and altering a network... | 04/01/2008 |
| 7353491 | Optimization of memory accesses in a circuit design Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset... | 04/01/2008 |
| 7353496 | Storage controller software development support system and software development support method In the present invention, the scope and degree of the effect of hardware alterations on software is grasped, and development is performed while making coordination between software and hardware. The storage system comprises a plurality of hardware elements and a plu... | 04/01/2008 |
| 7353473 | Modeling small mosfets using ensemble devices A method of modeling statistical variation of field effect transistors having fingers physically measures characteristics of existing transistors and extracts a scaled simulation based on the characteristics of the existing transistors using a first model. The metho... | 04/01/2008 |
| 7353489 | Determining hardware parameters specified when configurable IP is synthesized An attribute of a hardware feature to be customized in a soft core is parameterized so that a value received from a user can be used to generate a description of a circuit containing the customized hardware feature. The generated description also describes, in accor... | 04/01/2008 |
| 7352192 | Method and relative test structure for measuring the coupling capacitance between two interconnect lines A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit... | 04/01/2008 |
| 7353159 | Method for parallel simulation on a single microprocessor using meta-models The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N... | 04/01/2008 |
| 7353155 | System and method for automatic selection of transmission line macromodels Transmission line macromodels can be classified into main categories of delay-extraction and rational approximation. The exponential solution of the Telegrapher's Equation is used to create a system and method that enable a time-domain circuit simulator to automatic... | 04/01/2008 |
| 7353162 | Scalable reconfigurable prototyping system and method A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customiz... | 04/01/2008 |
