Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7844438 | Method to analyze and correct dynamic power grid variations in ICs A method to analyze and correct dynamic power grid variations in an IC includes performing a dynamic power grid analysis of the circuit, identifying an excessive dynamic power grid voltage fluctuation from the analysis, and modifying the circuit to reduce the excess... | 11/30/2010 |
| 7844437 | System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit A system and method for matching the hardware resource requirements of a user module with the available resources of an underlying integrated circuit is shown. Databases are utilized to describe the requirements of a particular user module and the resources of a par... | 11/30/2010 |
| 7835897 | Apparatus and method for connecting hardware to a circuit simulation A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware perip... | 11/16/2010 |
| 7835896 | Apparatus for evaluating and demonstrating electronic circuits and components A new system for simulation of electrical circuits and devices over a network is disclosed. The system consists of at least a client computer, a server computer, a network that connects them (including intermediate proxy servers and routers) and software methods. Ne... | 11/16/2010 |
| 7827020 | Post initial microcode load co-simulation Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial microcode load) state, and transferring the post-initial microcode state from... | 11/02/2010 |
| 7827018 | Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements... | 11/02/2010 |
| 7827019 | Method for order selection in passive transmission line macromodels based on the lie criteria A passive macromodel for lossy, dispersive multiconductor transmission lines uses a multiplicative approximation of the matrix exponential known as the Lie product. The circuit implementation of the macromodel is a cascade of elementary cells, each cell being the co... | 11/02/2010 |
| 7827017 | Method and system for implementing circuit simulators A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping con... | 11/02/2010 |
| 7822589 | Method and apparatus for automatic generation of multiple integrated circuit simulation configuration A software-based development tool is operative to automatically determine an appropriate simulation configuration for a multistage switch fabric or other multiple circuit element electronic system. The development tool includes an interface permitting user control o... | 10/26/2010 |
| 7822590 | Method and system for implementing, controlling, and interfacing with circuit simulators A system and method for performing circuit simulation is described. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals a... | 10/26/2010 |
| 7822591 | Logic circuit model conversion apparatus and method thereof; and logic circuit model conversion program A logic circuit model conversion apparatus includes a first analysis unit which analyzes a model in which a logic circuit of a register transfer level has been coded and outputs simultaneous blocks and an analysis result, a creating unit which creates a common execu... | 10/26/2010 |
| 7818158 | Method for symbolic simulation of circuits having non-digital node voltages In a computer simulation of an analog device in a digital circuit, a piece-wise linear lookup table is used to determine the channel resistance of the transistors in the analog device, allowing the node voltages to take on non-digital values. The piece-wise linear l... | 10/19/2010 |
| 7818157 | Instantaneous voltage drop sensitivity analysis tool (IVDSAT) A method for analyzing an electrical characteristic of wire segments configured as one or more power meshes in an integrated circuit (IC) core comprising the steps of (A) specifying design information corresponding to the power meshes, (B) specifying at least one ty... | 10/19/2010 |
| 7813908 | Clock control module simulator and method thereof A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock co... | 10/12/2010 |
| 7809542 | System and method for glitch analysis in circuits A system and method for analyzing power glitch in circuits includes simulating a circuit to provide waveform responses at positions of interest in the circuit. Each waveform response is processed to determine glitch power by comparing optimal energy to actual energy... | 10/05/2010 |
| 7801718 | Analyzing timing uncertainty in mesh-based architectures A method of analyzing timing uncertainty involves creating an accurate model of one or more circuit elements of a mesh circuit residing within a window that covers a subset of the mesh circuit. An approximate model of one or more circuit elements of the mesh circuit... | 09/21/2010 |
| 7801717 | Method for smart dummy insertion to reduce run time and dummy count A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inse... | 09/21/2010 |
| 7788078 | Processor/memory co-exploration at multiple abstraction levels Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may includ... | 08/31/2010 |
| 7788079 | Methods for producing equivalent circuit models of multi-layer circuits and apparatus using the same A method and an apparatus for obtaining an equivalent circuit model of a multi-layer circuit are disclosed. The method includes simulating the multi-layer circuit using an electromagnetic field analysis to provide a coupling network; and simplifying the coupling net... | 08/31/2010 |
| 7783466 | IC chip parameter modeling A method and system are disclosed for preserving measured temperature and geometric behavior of a hardware model while adjusting the model to match specified target values. In one embodiment, the method includes measuring a characteristic of an integrated circuit (I... | 08/24/2010 |
| 7783465 | Parallel multi-rate circuit simulation A computer-implemented method for solving parallel equations in a circuit simulation is described. The method includes partitioning a circuit Jacobian matrix into loosely coupled partitions, reordering the voltage vector and the matrix according to the partitions, a... | 08/24/2010 |
| 7783464 | Card for simulating peripheral component interconnect loads A card for simulating peripheral component interconnect (PCI) loads includes an interface configured for electrically connecting to a motherboard and a load circuit configured for simulating the different loads. The load circuit comprises at least one power module r... | 08/24/2010 |
| 7778812 | Selecting data to verify in hardware device model simulation test generation Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate th... | 08/17/2010 |
| 7774186 | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and indu... | 08/10/2010 |
| 7761276 | Apparatus and method for port reduction in simulation files Various port reduction methods are employed to reduce the number of port definitions in a simulation file. A ground port reduction method is first employed to reduce certain power supply reference connections to an absolute ground reference for the circuit model. Ne... | 07/20/2010 |
| 7761277 | System and method for improved logic simulation using a negative unknown boolean state A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The in... | 07/20/2010 |
| 7761275 | Synthesizing current source driver model for analysis of cell characteristics A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and o... | 07/20/2010 |
| 7761274 | Temperature-based clock frequency controller apparatus and method A temperature-based clock frequency controller is implemented in an integrated circuit such as a microprocessor. The temperature-based clock frequency controller includes a register to store a threshold temperature value, a thermal sensor, and clock adjustment logic... | 07/20/2010 |
| 7761278 | Semiconductor device stress modeling methodology A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base... | 07/20/2010 |
| 7756695 | Accelerated simulation and verification of a system under test (SUT) using cache and replacement management tables A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Ma... | 07/13/2010 |
| 7747425 | System and method for peak current modeling for an IC design A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for ... | 06/29/2010 |
| 7742909 | Reconstruction of data from simulation models Systems and media for reconstructing data from simulation models are disclosed. Embodiments may include a media containing instructions for accessing an alias from an alias file. The media may include instructions for searching for a net name and, if the net name is... | 06/22/2010 |
| 7742907 | Iterative abstraction using SAT-based BMC with proof analysis A method of obtaining a resolution-based proof of unsatisfiability using a SAT procedure for a hybrid Boolean constraint problem comprising representing constraints as a combination of clauses and interconnected gates. The proof is obtained as a combination of claus... | 06/22/2010 |
| 7742908 | Method for simulating an electrical circuit by synthesis of a physical model, device for simulating an electrical circuit, in particular a musical instrument obtained with that method Method for simulation of an electrical circuit by synthesis of a physical model, using digital wave structures including the following steps: within the framework of digital wave structure, consider a serial and parallel adapter block with at least three ports of wh... | 06/22/2010 |
| 7739094 | Method and apparatus for designing an emulation chip using a selectable fastpath topology A method and apparatus for designing a processor-based emulation integrated circuit (chip) having a selectable fastpath topology. Included are initially designing an N-level fastpath topology comprising a plurality of processors, then reducing the N-level fastpath t... | 06/15/2010 |
| 7739095 | Method for determining best and worst cases for interconnects in timing analysis Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signa... | 06/15/2010 |
| 7739093 | Method of visualization in processor based emulation system A processor-based emulation system for emulating an integrated circuit design, the processor-based emulation system including emulation circuitry and capture circuitry. The capture circuitry is operable to capture processing results from the emulation circuitry. The... | 06/15/2010 |
| 7729896 | Cycle simulation method, cycle simulator, and computer product It is determined whether an i-th instruction is for a memory access. If the i-th instruction is the memory access, it is determined whether an address to access according to the i-th instruction coincides with an address that has been accessed by a first execution b... | 06/01/2010 |
| 7720663 | Delay analysis system The present invention provides a delay analysis system which makes it possible to make delay analysis considering circuit logical information in order to give more accurate delay times. In addition to circuit connection information and delay time information on the ... | 05/18/2010 |
| 7711535 | Simulation of hardware and software A method and apparatus are provided to allow co-verification of hardware and software elements asynchronously from a programmable logic device (PLD). ... | 05/04/2010 |
