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| Number | Title | Issue Date |
| 7331027 | Method for swapping circuits in a metal-only engineering change A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running ... | 02/12/2008 |
| 7331030 | Method to unate a design for improved synthesizable domino logic flow A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthes... | 02/12/2008 |
| 7331031 | Method for describing and deploying design platform sets A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design plat... | 02/12/2008 |
| 7330808 | Dummy block replacement for logic simulation A method (10) of reducing a size of a netlist for a target architecture can include the steps of creating (12) a netlist of objects for the target architecture, identifying (14) objects specific to the target architecture that are repeated regul... | 02/12/2008 |
| 7330837 | Method for adapting a software product to an environment A method for adapting a software product to an environment is provided tat comprises providing the software product with a first portion of code including instructions for performing a predetermined function. At least one aspect of performing the predetermined funct... | 02/12/2008 |
| 7331032 | Computer-aided design system to automate scan synthesis at register-transfer level A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL tes... | 02/12/2008 |
| 7328143 | Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened representation; 2) generating a primitive database using the source file, whe... | 02/05/2008 |
| 7328195 | Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model A method is taught for increasing the steady-state verification speed of analog and mixed signal design through increased simulation speed, model abstraction by probing an existing component model or actual device and formal comparison of distinct component models. | 02/05/2008 |
| 7324982 | Method and apparatus for automated debug and optimization of in-circuit tests A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge fram... | 01/29/2008 |
| 7325182 | Method and circuit arrangement for testing electrical modules The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The c... | 01/29/2008 |
| 7325210 | Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for t... | 01/29/2008 |
| 7323862 | Apparatus and method for detecting photon emissions from transistors A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the... | 01/29/2008 |
| 7324562 | Method and apparatus for introducing differential delay between virtually concatenated tributaries In one embodiment, the invention is an apparatus for testing differential delay correction of network elements using virtual concatenation. The apparatus includes a first PRBS (pseudo-random bit stream) generator dedicated to a first tributary. The apparatus also in... | 01/29/2008 |
| 7324932 | Virtual test environment A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emul... | 01/29/2008 |
| 7321882 | Method for supervised teaching of a recurrent artificial neural network A method for the supervised teaching of a recurrent neutral network (RNN) is disclosed. A typical embodiment of the method utilizes a large (50 units or more), randomly initialized RNN with a globally stable dynamics. During the training period, the output units of ... | 01/22/2008 |
| 7322015 | Simulating a dose rate event in a circuit design Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation o... | 01/22/2008 |
| 7319947 | Method and apparatus for performing distributed simulation utilizing a simulation backplane A method and apparatus for performing distributed simulation is presented. According to an embodiment of the present invention, simulators are interfaced to a simulation backplane via simulator-dependent interfaces (SDI's). The simulators exchange messages via the s... | 01/15/2008 |
| 7319946 | Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core ... | 01/15/2008 |
| 7320116 | Method of generating cell library data for large scale integrated circuits A method of generating library data for a cell constructed of interconnected MOS transistors, includes a resistance extraction step which extracts source and drain resistances according to source and drain region surface areas by using a resistance calculating formu... | 01/15/2008 |
| 7320118 | Delay analysis device, delay analysis method, and computer product A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that compute... | 01/15/2008 |
| 7319367 | Programmable oscillators for high frequency clock generation for simulation environments A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring osc... | 01/15/2008 |
| 7318207 | Apparatus and method for verifying layout interconnections using power network analysis A method for verifying layout interconnections includes extracting a loop circuit as a loop portion in a first circuit model. The first circuit model includes first branch interconnections included in the loop portion and second branch interconnections, first nodes,... | 01/08/2008 |
| 7318213 | Apparatus, method and program for behavioral synthesis including loop processing A behavioral synthesis apparatus includes a control data flow graph generator that generates a CDFG specifying an execution order of calculations written in a behavior description including an external loop processing that includes internal loops processing which do... | 01/08/2008 |
| 7318014 | Bit accurate hardware simulation in system level simulators A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the comp... | 01/08/2008 |
| 7318228 | System and method for task arbitration in multi-threaded simulations Present herein is a system and method for arbitration in multi-threaded programming. Task calls are directed to a task wrapper that associates the task call with a particular unique identifier, and stores parameters provided by the task call at memory locations asso... | 01/08/2008 |
| 7318205 | Measure of analysis performed in property checking The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constrain... | 01/08/2008 |
| 7317959 | System and method for modeling and/or executing software applications, especially MES applications The invention relates to a system and a method for modelling and executing business processes in MES systems (manufacturing execution systems) or manufacturing control systems by means of a plurality of independently operating processes which are modelled by automat... | 01/08/2008 |
| 7315993 | Verification of RRAM tiling netlist The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. ... | 01/01/2008 |
| 7315802 | Methods of logic reduction in electrical circuits utilizing fault simulation Methods of reducing the amount of logic in a digital circuit without affecting the functionality of the circuit. A circuit description and one or more test patterns are supplied to a fault simulator. The fault simulator runs the test patterns on the circuit, and ide... | 01/01/2008 |
| 7315803 | Verification environment creation infrastructure for bus-based systems and modules A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for... | 01/01/2008 |
| 7315973 | Method and apparatus for choosing tests for simulation and associated algorithms and hierarchical bipartite graph data structure An apparatus for and method of generating test cases for testing simulated logic circuit designs. The test cases are basically generated automatically in a random fashion, manually, or using some combination of automatic and manual techniques. Each test case has a c... | 01/01/2008 |
| 7315992 | Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migrati... | 01/01/2008 |
| 7315991 | Compiling HLL into massively pipelined systems A method of creating a circuit from a high level programming language (HLL) program can include generating a netlist from the HLL program, wherein the netlist specifies the circuit design (1320, 1325). The circuit design can be run within a programmable logic... | 01/01/2008 |
| 7313635 | Method and apparatus for simulating a load on an application server in a network A method is disclosed for simulating a load on an application server in a network. The method intercepts data packets of a request from a sender to a receiver. The data packets to be intercepted can be selected according to specified criteria, such as communications... | 12/25/2007 |
| 7313508 | Process window compliant corrections of design layout The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the ... | 12/25/2007 |
| 7313509 | Simulation method and apparatus, and computer-readable storage medium A simulation method makes a noise analysis based on parameters including a conductor resistance which takes skin effect into consideration. The simulation method calculates a first resistance of one of conductors having a largest cross sectional area, obtains a pred... | 12/25/2007 |
| 7313731 | Systems and methods for identifying erroneous transactions Disclosed are systems and methods for identifying erroneous transactions. In one embodiment, a system and a method pertain to monitoring an interface, determining information related to termination of a test case, and after the test case has terminated, identifying ... | 12/25/2007 |
| 7313510 | Methods for estimating power requirements of circuit designs One embodiment of the present invention is a method for estimating a power requirement of a circuit design that includes steps of: (a) selecting a set of targeted Energy Arcs and/or Power Arcs; (b) creating one or more circuit states using the set of targeted Energy... | 12/25/2007 |
| 7313773 | Method and device for simulator generation based on semantic to behavioral translation Generating a simulator from an architecture description. A target architecture model described in an architecture description language (ADL) is accessed. The model comprises a semantic representation of an instruction set for the target architecture. The semantic re... | 12/25/2007 |
| 7310795 | Method and apparatus for simulating logic circuits that include a circuit block to which power is not supplied A logic circuit simulation apparatus used in designing a logic IC (integrated circuit) is provided. The logic circuit simulation apparatus includes a power control signal specifying unit which creates power control signal information for specifying statuses of a plu... | 12/18/2007 |
