Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 8190418 | Producing integrated circuits with time-dependent-impedance elements Methods, systems and computer programs for producing integrated circuits (IC) that contain an electronic component with time-dependent impedance are provided. According to one method, time-dependent impedance values for the electronic component are obtained. These t... | 05/29/2012 |
| 8185369 | Method and apparatus for characterizing properties of electronic devices depending on device parameters A system and method for obtaining information about an electronic device includes the steps of providing a criterion for a property of the electronic device depending on at least one device parameter, and determining a relationship between variations of the at least... | 05/22/2012 |
| 8180620 | Apparatus and method for performing hardware and software co-verification testing Verification tests perform hardware and software co-verification on a system under verification. Each signal interface controller coupled to the system performs a test action transferring at least one of stimulus signals and response signals between a corresponding ... | 05/15/2012 |
| 8180621 | Parametric perturbations of performance metrics for integrated circuits A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal conditio... | 05/15/2012 |
| 8176463 | Modeling and simulating device mismatch for designing integrated circuits A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evalu... | 05/08/2012 |
| 8175862 | Model-based systems and methods for monitoring resources Modeling systems and methods for constructing one or more models of a computing system using collected data. Certain model-based systems build topology models and/or model instances by transforming collected performance data into a collection-location independent fo... | 05/08/2012 |
| 8176450 | Method and apparatus for parameterizing hardware description language code in a system level design environment A method for managing an electronic design automation tool includes importing a component. A graphical user interface is generated to allow a user to enter values for parameters of the component. Other embodiments are disclosed. ... | 05/08/2012 |
| 8170857 | In-situ design method and system for improved memory yield A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations ... | 05/01/2012 |
| 8170856 | Systems and methods for real-time advanced visualization for predicting the health, reliability and performance of an electrical power system A system for real-time three-dimensional (3D) visualization of an electrical system is disclosed. The system includes a data acquisition component, a power analytics server and a client terminal. The data acquisition component acquires real-time data output from the... | 05/01/2012 |
| 8170858 | Characterization and modeling of ferroelectric capacitors Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. ... | 05/01/2012 |
| 8166425 | Validating circuit simulation results A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting too... | 04/24/2012 |
| 8166432 | Timing verification method and timing verification apparatus Timing verification method includes processes wherein timing analysis is performed taking voltage drop of a laid out circuit into consideration and a changing instruction list for changing the laid out circuit is produced based on a result of the timing analysis. Th... | 04/24/2012 |
| 8165865 | Modeling and simulation method A method for modeling and simulating a system comprising first and second interrelated components is disclosed. The method comprises modeling the behavior of said first and second components using first and second specifications. Each of said first and second specif... | 04/24/2012 |
| 8165864 | Method, system and computer program product for verifying address generation, interlocks and bypasses Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagati... | 04/24/2012 |
| 8160858 | Systems and methods of efficient library characterization for integrated circuit cell libraries A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality... | 04/17/2012 |
| 8160856 | Using a serial profiler to estimate the performance of a parallel circuit simulation Some embodiments of the present invention provide a system that profiles a serial simulation of a circuit to estimate the performance of a parallel simulation of the circuit. During operation, the system profiles execution of module instances during a serial simulat... | 04/17/2012 |
| 8161445 | Logic transformation and gate placement to avoid routing congestion A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic ... | 04/17/2012 |
| 8160857 | Selective compilation of a simulation model in view of unavailable higher level signals In response to receiving HDL file(s) that specify a plurality of hierarchically arranged design entities defining a design to be simulated and that specify an instrumentation entity for monitoring simulated operation of the design, an instrumented simulation executa... | 04/17/2012 |
| 8161438 | Determining mutual inductance between intentional inductors Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the ... | 04/17/2012 |
| 8156457 | Concurrent simulation of hardware designs with behavioral characteristics Simulating hardware includes generating a data flow representation of the hardware, based on a hardware description language (HDL) description. The data flow representation including compatibility information that preserves behavioral and synthesizable characteristi... | 04/10/2012 |
| 8150672 | Structure for improved logic simulation using a negative unknown boolean state A system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown Boolean state is provided. When the circuit is simulated, one or more initial simulated logic elements are initialized to the unknown Boolean state. The in... | 04/03/2012 |
| 8151230 | Blended model interpolation According to the illustrative embodiments, a data structure is accessed to determine a set of known data points surrounding a queried data point having an input value and an output value, the set of known data points including first, second and third data points. Fi... | 04/03/2012 |
| 8145466 | Clustering of electronic circuit design modules for hardware-based and software-based co-simulation platforms Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first c... | 03/27/2012 |
| 8140313 | Techniques for modeling variables in subprograms of hardware description language programs A method, system and computer program product for modeling variables in subprograms of a HDL program. A subprogram is provided with an initial value of a variable of an element being modeled and the subprogram is stored in memory of a data processing system. In resp... | 03/20/2012 |
| 8140314 | Optimal bus operation performance in a logic simulation environment Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable re... | 03/20/2012 |
| 8140315 | Test bench, method, and computer program product for performing a test case on an integrated circuit The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference... | 03/20/2012 |
| 8136057 | Semiconductor device manufacturing method, data generating apparatus, data generating method and recording medium readable by computer recorded with data generating program A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a sim... | 03/13/2012 |
| 8136064 | Bijectively mapping character string to integer values in integrated circuit design data A data processor which includes: a circuit data providing section which provides circuit data including a character string; a replacement section which bijectively maps the character string of the provided circuit data to integer values; and a data developer which e... | 03/13/2012 |
| 8132137 | Prediction of dynamic current waveform and spectrum in a semiconductor device A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. In one embodiment, the timing chara... | 03/06/2012 |
| 8121826 | Graphical user interface for system design A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the s... | 02/21/2012 |
| 8121825 | Method and apparatus for executing a hardware simulation and verification solution One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can inclu... | 02/21/2012 |
| 8117568 | Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating t... | 02/14/2012 |
| 8112264 | Simulating circuits using network tearing A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, find... | 02/07/2012 |
| 8108194 | Peak power detection in digital designs using emulation systems A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emula... | 01/31/2012 |
| 8099270 | Simulation model for transistors Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model. ... | 01/17/2012 |
| 8099693 | Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit design Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes t... | 01/17/2012 |
| 8099269 | Two-step simulation methodology for aging simulations The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are store... | 01/17/2012 |
| 8095352 | System and method for automatic selection of transmission line macromodels Transmission line macromodels can be classified into main categories of delay-extraction and rational approximation. The exponential solution of the Telegrapher's Equation is used to create a system and method that enable a time-domain circuit simulator to automatic... | 01/10/2012 |
| 8095353 | Power index computing apparatus, method of computing power index, and computer product A power index computing apparatus that computes a power index for a circuit having one or more modules includes an obtaining unit that obtains estimated power consumption for a module in the circuit and a first computing unit that computes entropy based on a transit... | 01/10/2012 |
| 8095351 | Modeling method, apparatus, and computer readable medium for creating three-dimensional analysis model of a target object to analyze data transmission A modeling method creates a three-dimensional analysis model of a target object for extracting parameters that are used to analyze a high-frequency transmission, by selecting, from an art work data of the target object, an extraction target region that becomes a tar... | 01/10/2012 |
