Bizarre Patents
Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 8190416 | Computer network management According to one embodiment of the present invention, there is provided a method of identifying components of a computer infrastructure, comprising building a graph-based model of at least a part of the computer infrastructure, determining the presence within the bu... | 05/29/2012 |
| 8190415 | Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of th... | 05/29/2012 |
| 8190417 | Real time simulating method and system using a sequence diagram System for simulating sub-systems of a tested system includes: (a) a sequence diagram storage defining the intercommunication of messages between various sub-systems of a real system; (b) an indicator for the sequence diagram those missing sub-systems, which have to... | 05/29/2012 |
| 8185865 | Methods for gate-length biasing using annotation data Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtain... | 05/22/2012 |
| 8185368 | Mixed-domain analog/RF simulation A simulation environment is disclosed wherein both analog and RF signals are simulated in a single flow by a mixed-domain simulator. The simulator includes a simulator kernel with an analog solver and an RF solver to allow both analog- and RF-type of signals to be s... | 05/22/2012 |
| 8180616 | Component tracing in a network packet processing device Approaches for gathering packet processing information. A directed graph is used to represent the packet processing system. In response to each network packet input to the system, an associated, unique packet identifier is established for the network packet. Each in... | 05/15/2012 |
| 8180619 | System and method for digital effects analysis An analysis tool analyzes a model to determine the digital effect of the model in a modeling or programming environment. With the analysis tool, a user can determine minimum hardware functionality needed to execute the software generated from the model. The hardware... | 05/15/2012 |
| 8180618 | Method and system for inductor power loss analysis Described herein are embodiments of a method and system for determining power loss in an inductor. In accordance with one aspect, a method is provided of determining power loss in an inductor. The method comprises modeling an inductor's windings and core using elect... | 05/15/2012 |
| 8180617 | Computer-based computational tools for use in electrophysiology Computer-based computational tools for use in determining spatial charge distributions for biological systems that include one or more biological membranes are provided. At least one of the biological membrane includes at least two regions having different electrica... | 05/15/2012 |
| 8176455 | Semiconductor device design support apparatus and substrate netlist generation method A semiconductor device design support apparatus for generating a substrate netlist so as to be able to perform substrate noise analysis with high accuracy in a short time. The semiconductor device design support apparatus comprises a unit that divides a semiconducto... | 05/08/2012 |
| 8175861 | Machining simulation method and machining simulation apparatus A machining simulation apparatus is arranged in a machine tool having a tool holding mechanism, a workpiece holding mechanism, a drive mechanism and a numerical controller, and provided with: an actual CCD camera for imaging a tool held by the tool holding mechanism... | 05/08/2012 |
| 8170854 | Behavioral model generation A model of a device is generated. An input port of the device is stimulated with a large amplitude signal having a central frequency. A first port of the device is perturbed with a small amplitude signal tone. The small amplitude signal tone is at a frequency offset... | 05/01/2012 |
| 8170855 | System for simulating PET gantry A system for simulating a Positron Emission Tomography (PET) gantry has a computer system having a bus system for receiving expansion cards, a mass data storage support system, the mass storage system being operable to store coincidence-event and tag packet data, an... | 05/01/2012 |
| 8166438 | Low RC local clock distribution A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The ... | 04/24/2012 |
| 8165863 | Visualization method for electrical machine operation models based on mechanical machine operation models A visualization of an electrical machine operation model of logic controller behavior is displayed on a display such as a two-dimensional computer display. The display includes separate spaces representing separate devices in the model. For each device, several char... | 04/24/2012 |
| 8165861 | Printed circuit analysis method and device A simulation method of an electronic circuit or a printed circuit, represented in the form of masks and connections, includes the definition of, on one hand, inputs and outputs of circuit networks, and, on the other, internal components of each network; the formatio... | 04/24/2012 |
| 8165862 | Methods and systems for predicting application performance A method for identifying and evaluating potential computer network configuration problems as related to deployment of one or more computer applications accessed via an associated computer network architecture is described. The method includes emulating the computer ... | 04/24/2012 |
| 8160855 | System and method for simulating network attacks A method of simulating network activities includes building a model of the network, the model including data retrieved over a predetermined period of time. The method further includes running a plurality of queries against the model to determine their impacts on the... | 04/17/2012 |
| 8156458 | Uniquification and parent-child constructs for 1xN VLSI design Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and cre... | 04/10/2012 |
| 8150671 | Portable USB power mode simulator tool A simulation tool includes a printed circuit board assembly or PCBA having a built-in USB communication port and a microcontroller. A host computer transmits user-selected configuration data to the microcontroller, which transforms the data into solid-state signals.... | 04/03/2012 |
| 8150670 | Simulator and simulation method An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simula... | 04/03/2012 |
| 8146047 | Automation method and system for assessing timing based on gaussian slack An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functio... | 03/27/2012 |
| 8146043 | Huygens' box methodology for signal integrity analysis A method for performing a signal integrity analysis on an integrated circuit (IC) that includes a plurality of scatterers by dividing the scatterers into subgroups using a nested Huygens' equivalence principle algorithm and solving a set of equations realized thereb... | 03/27/2012 |
| 8146041 | Latch based optimization during implementation of circuit designs for programmable logic devices A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed u... | 03/27/2012 |
| 8135570 | Generation of code from a graphical model A method and system are provided for generating code from a graphical model in a graphical modeling environment. The graphical model includes at least one signal having a data size, a data dimensionality, or both that can vary from a first time instance to a second ... | 03/13/2012 |
| 8135571 | Validating manufacturing test rules pertaining to an electronic component The invention is directed to validating a specified manufacturing test rule, which pertains to an electronic component. The method includes generating a file of test data sets, wherein each test data set in the file is valid for the rule. Each test data set includes... | 03/13/2012 |
| 8126693 | Method and system for modeling, validating and automatically resolving goals and dependencies between elements within a topology Computer implemented method, system and computer usable program code for configuring a computing system. A system for configuring a computing system includes a mechanism for creating a model of a computing system, a validator for determining whether there are any er... | 02/28/2012 |
| 8126691 | System and method for block diagram simulation context restoration A method of saving portions of a simulation or execution engine image at various points in a simulation or execution is disclosed. The saving of the simulation or execution context in addition to the more traditional saving of the system state information enables th... | 02/28/2012 |
| 8126692 | Method and system for modeling, validating and automatically resolving goals and dependencies between elements within a topology Computer implemented method, system and computer usable program code for configuring a computing system. A determination is made whether there are any errors in the model, and responsive to determining that there is at least one error in the model, a determination i... | 02/28/2012 |
| 8127266 | Gate-length biasing for digital circuit optimization Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes ... | 02/28/2012 |
| 8126694 | Modeling conductive patterns using an effective model A model of a sample with a periodic or non-periodic pattern of conductive and transparent materials is produced based on the effect that the pattern has on TE polarized incident light. The model of the pattern may include a uniform film of the transparent material a... | 02/28/2012 |
| 8126695 | Systems and methods for event based execution of fieldbus process control strategies Systems (200, 230, 240) and methods (400) for event based execution of a Fieldbus process control strategy (FPCS) for simulation of an industrial process at least partially implemented by a Fieldbus system including a FIM (114, 116, 212, 214, 232, 2... | 02/28/2012 |
| 8127259 | Synthesis constraint creating device, behavioral synthesis device, synthesis constraint creating method and recording medium A synthesis constraint creating unit has a process emergence number acquiring unit that acquires, for each process attribute, the emergence number of the process belonging to each process attribute, the process being in the behavior level description, a circuit stru... | 02/28/2012 |
| 8121824 | Predicate checking for distributed systems Predicate checking in conjunction with distributed systems can enable an investigating user to check predicates in the context of instance states and/or distributed states of a distributed system. In an example embodiment, a method entails accepting distributed syst... | 02/21/2012 |
| 8117577 | Determining timing paths within a circuit block of a programmable integrated circuit A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a m... | 02/14/2012 |
| 8112263 | Method for logic checking to check operation of circuit to be connected to bus To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted ... | 02/07/2012 |
| 8112261 | Methods and simulation tools for predicting GPS performance in the broad operating environment To facilitate GPS hardware selection and evaluate performance of vehicle integrated GPS hardware, including various types of GPS antennas and receivers, within different vehicle operating environments, embodiments of the invention are used to provide a simulator whi... | 02/07/2012 |
| 8112262 | Service modeling and virtualization The systems and methods described herein can be used to provide virtual service environments. In one embodiment, a virtual service model is generated by detecting one or more transactions, each of which includes a request sent from a requester to a software service ... | 02/07/2012 |
| 8108193 | Collaboration framework for modeling A modeling solution, which enables various users to create, use, and evaluate models, such as scientific models, in various scenarios is provided. To this extent, the modeling solution can define a model using one or more model components, each of which is configure... | 01/31/2012 |
| 8108822 | Methodology for placement based on circuit function and latchup sensitivity A structure, apparatus and method for circuits to minimize sensitivity to latch. The method includes, for example, identifying element density of at least one functional circuit block and element attributes of elements associated with the at least one functional cir... | 01/31/2012 |
