Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7193801 | Method and apparatus for testing a servo circuit of a read/write head system A test pattern generator for generating test patterns for testing a servo circuit of a read/write head system. The pattern generator uses a relatively simple encoding technique to produce test patterns that have peaks with phase characteristics similar or identical ... | 03/20/2007 |
| 7194390 | Predictor of minimal noise figure for wideband amplifier A predictor allows the computation of the greatest lower bound of the noise figure pertaining uniformly over the operating band of a wideband amplifier. This computation is done directly from noise-parameter data of the amplifier. ... | 03/20/2007 |
| 7190157 | Method and apparatus for layout independent test point placement on a printed circuit board A layout independent test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to various locations along a trace at a test access point... | 03/13/2007 |
| 7191072 | Pressure and temperature measurement of a piezo-resistive device using differential channel of a ratiometric analog to digital converter A temperature and pressure measuring circuit is provided. The circuit comprises an uncompensated pressure transducer, an analog-to-digital converter, a reference resistive device, and first and second switches. The transducer has variable resistive devices between f... | 03/13/2007 |
| 7191085 | Method for testing an electric circuit In a method for testing an electric circuit, a first circuit is produced by a first process sequence. A first signal is applied to the first circuit and a signal indicating if the first circuit is defective is generated by comparing the first signal with the first c... | 03/13/2007 |
| 7190155 | Test apparatus and testing method There is provided a test apparatus for testing a device-under-test, having a reference clock source for generating reference clock for controlling operations of the device-under-test, a clock regenerating circuit for generating, based on a phase adjusting signal to ... | 03/13/2007 |
| 7188044 | World-wide distributed testing for integrated circuits An integrated circuit test method is provided that utilizes shared tester resources physically located at different geographical sites throughout the world to test specific integrated circuits, thereby maximizing utilization of all tester resources and, thereby, dra... | 03/06/2007 |
| 7188043 | Boundary scan analysis A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors ... | 03/06/2007 |
| 7188291 | Circuit and method for testing a circuit having memory array and addressing and control unit A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in... | 03/06/2007 |
| 7187192 | Semiconductor test device having clock recovery circuit A semiconductor test device for acquiring a multiplexed clock signal from LSI output data and using the clock to test the LSI. The device includes a time interpolator and registers connected in series. The time interpolator has flip-flops connected in parallel for r... | 03/06/2007 |
| 7184919 | Dynamic routing for a measurement system System and method for performing dynamic routing in a measurement system to perform a measurement task. The system includes a computer and one or more measurement devices. One or more topography descriptions (TD) representing connectivity between devices and/or devi... | 02/27/2007 |
| 7185247 | Pseudo bus agent to support functional testing Methods, systems, and apparatuses are provided to emulate bus transactions for a device under test (DUT). Test data is sent from a testing device to a cache of a DUT. When data needs to be read or written to locations outside of the cache (e.g., bus action is needed... | 02/27/2007 |
| 7183791 | Reliability circuit for applying an AC stress signal or DC measurement to a transistor device An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditi... | 02/27/2007 |
| 7184916 | Apparatus and method for testing memory cards A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to b... | 02/27/2007 |
| 7183785 | Test system and method for reduced index time A system for testing with an automated test equipment (ATE). The ATE includes a tester, an interface board connected to the tester, a first socket and a second socket of the interface board, a first manipulator arm connected to the tester, and a second manipulator a... | 02/27/2007 |
| 7184914 | Sensor signal processor A sensor signal processor includes a scale having optically or magnetically fine divisions; a detection sensor that moves with respect to the scale and that is provided in association with the divisions of the scale; and a position detecting unit for calculating pos... | 02/27/2007 |
| 7181146 | Self-adjusting data transmitter A self-adjusting data transmitter driver can be used for transmission of analog or digital data signal over any suitable communication channel, such as, for example, optical, electrical, wireless and satellite. The optical transmitter driver may be used to drive a s... | 02/20/2007 |
| 7180436 | Apparatus and method for auto calibration of display device An apparatus for auto calibration of a display device, the apparatus including a signal generating unit for generating predetermined digital patterns, converting the digital patterns into R, G, B and Y, U, V color signals, converting the color signals into analog pa... | 02/20/2007 |
| 7181716 | Method and apparatus for generating circuit model for static noise analysis A method and apparatus for generating a noise circuit model for an electronic circuit includes analyzing the electronic circuit to determine a first circuit parameter for a victim and aggressor circuits and a second circuit parameter for the aggressor circuits, orde... | 02/20/2007 |
| 7181359 | Method and system of generic implementation of sharing test pins with I/O cells The present invention provides a method and a system of generic implementation of sharing test pins with I/O cells. The method includes a step of making a general change in a testlib file. The testlib file is suitable for controlling I/O cell pins to gain test acces... | 02/20/2007 |
| 7181357 | Method and apparatus to calibrate thermometer Briefly, a processor and a method to calibrate a temperature reading of a digital thermometer. The calibration is done by using a first temperature value measured by an analog temperature sensor located at one point on the processor die and a second temperature valu... | 02/20/2007 |
| 7177783 | Shape based noise characterization and analysis of LSI The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approxi... | 02/13/2007 |
| 7177775 | Testable digital delay line A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value duri... | 02/13/2007 |
| 7178076 | Architecture of an efficient at-speed programmable memory built-in self test A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to the memory built in self test sequencer module and applying a march tes... | 02/13/2007 |
| 7178115 | Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logi... | 02/13/2007 |
| 7174279 | Test system with differential signal measurement A test system with easy to fabricate hardware to make measurements on differential signals. The two legs of a differential signal are applied to a comparator. A variable bias is introduced into the comparison operation. By taking multiple measurements with different... | 02/06/2007 |
| 7171638 | Methods of screening ASIC defects using independent component analysis of quiescent current measurements A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurement... | 01/30/2007 |
| 7171510 | On-chip observability buffer to observer bus traffic The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency,... | 01/30/2007 |
| 7168853 | Digital measuring system and method for integrated circuit chip operating parameters This invention relates to digitally measuring operating parameters, for example, temperature, within a semiconductor chip and making those measurements internally available to hardware, firmware, and software. ... | 01/30/2007 |
| 7171334 | Method and apparatus for synchronizing data acquisition of a monitored IC fabrication process There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for autonomously monitoring fabrication equipment, for example, integrated circuit fabrication equipment. In one embodiment of ... | 01/30/2007 |
| 7170169 | LGA socket with EMI protection A socket is provided which has an insulative housing surrounding a metal substrate. The substrate has an array of apertures which are located in spatially arranged order to accommodate the precise pattern desired for the device to be connected. Contact assemblies in... | 01/30/2007 |
| 7171324 | System and method for removing measurement errors from measurement systems A test system and method which utilizes a component data base that stores performance data for individual component of the system. The system and method can further provide for using data and information from one calibration procedure in connection with performing f... | 01/30/2007 |
| 7171508 | Dual port memory with asymmetric inputs and outputs, device, system and method An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory controller. The asymmetric memory interface further includes an asymmetric write data interface having a w... | 01/30/2007 |
| 7171333 | On-wafer method and apparatus for pre-processing measurements of process and environment-dependent circuit performance variables for statistical analysis An on-wafer method and apparatus for preprocessing measurements of process and environment-dependent circuit performance variables provides new techniques for yield/performance test and analysis. An on-wafer circuit calculates the sums of multiple exponentiations of... | 01/30/2007 |
| 7168029 | Method for testing a universal serial bus host controller A chip test method is suitable for testing a universal serial bus host controller. First, the host controller and the client device are individually set in a test mode. Next, the client device performs a client-side test preparation action. In addition, the host con... | 01/23/2007 |
| 7168003 | Method and apparatus for automating printer and printer driver diagnostics and repair A program checks for installed printers, asks the users to select printers to be tested, and then proceeds to test for communications with the printer, print spooling and driver integrity as well as the driver's appropriateness for the operating system and for langu... | 01/23/2007 |
| 7167016 | Operation mode setting circuit According to the present invention, there is provided an operation mode setting circuit comprising: a plurality of latch circuits each of which receives one of at least two bits contained in an operation mode setting signal for set... | 01/23/2007 |
| 7167197 | Apparatus and method to evaluate an illuminated panel An apparatus to evaluate an illuminated panel comprises a camera to acquire a real-time digital color image of the illuminated panel and a stored digital color image of a standard illuminated panel. A monitor is provided to alternately display the real-time image an... | 01/23/2007 |
| 7164998 | Method for determining programmable coefficients to replicate frequency and supply voltage correlation in an integrated circuit One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine grain delay systhesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of a... | 01/16/2007 |
| 7164995 | Differential termination and attenuator network for a measurement probe A differential termination and attenuator network receives a differential input signal having a DC common mode voltage. The network circuit includes input termination resistors coupled in parallel with corresponding resistive attenuator circuits. A monitoring circui... | 01/16/2007 |
