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| Number | Title | Issue Date |
| 7778790 | Semiconductor integrated circuit device and delay fault testing method A semiconductor integrated circuit device includes a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register. The first flip-flop of the plurality of flip-flops latches a first input signal in synchronization with a... | 08/17/2010 |
| 7774154 | Test unit and test apparatus In the digitizer, a plurality of ADCs convert a plurality of analogue signals output from the device to be tested, to digital signals, respectively. The processing circuit is configured as a software-independent circuit and processes a plurality of digital signals o... | 08/10/2010 |
| 7756664 | Test apparatus and measurement circuit There is provided a test apparatus for testing a device under test. The test apparatus includes a gradient adjusting section that separately adjusts a gradient of a rising edge of a signal under measurement which is output from the device under test and a gradient o... | 07/13/2010 |
| 7752004 | Method and apparatus for configuring plurality of devices on printed circuit board into desired test port configuration A system on a circuit board includes a plurality of devices designed to access an electronic system on the circuit board, and a programmable logic device (PLD) connected to the plurality of devices. Each of the plurality of devices complies with a test port architec... | 07/06/2010 |
| 7734442 | Apparatus and method for a test and measurement instrument The apparatus for a test and measurement instrument consists of multiple integrated circuits with each integrated circuit being connected to its own memory controller. At least one of the integrated circuits is a specialized integrated circuit, which may be a graphi... | 06/08/2010 |
| 7729878 | Air bridge structures and methods of making and using air bridge structures A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic devi... | 06/01/2010 |
| 7729877 | Method and system for logic verification using mirror interface Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead... | 06/01/2010 |
| 7725283 | Methods and apparatus for a virtual test cell A method for calibrating a physical test cell includes the steps of: determining a set of inputs to be provided to the physical test cell based in part on a set of historical test data; providing the inputs to the physical test cell and receiving a set of outputs as... | 05/25/2010 |
| 7716003 | Model-based measurement of semiconductor device features with feed forward use of data for dimensionality reduction The present application discloses a new technique which reduces the dimensionality of a feature model by re-use of data that has been obtained by a prior measurement. The data re-used from the prior measurement may range from parameters, such as geometrical dimensio... | 05/11/2010 |
| 7711512 | System and method for testing semiconductor device According to an example embodiment, a semiconductor device test system includes a semiconductor device and a test apparatus. The semiconductor device includes a plurality of function blocks for performing predetermined functions at different operating speeds and a p... | 05/04/2010 |
| 7706999 | Circuit testing apparatus The invention discloses a circuit testing apparatus for testing a device under test. The circuit testing apparatus includes a precision measurement unit, a signal transformation module, and a microprocessor. The precision measurement unit is coupled to the device un... | 04/27/2010 |
| 7698087 | Semiconductor integrated circuit and testing method of same A program circuit activates a pass signal when a first program unit is programmed. The first program unit is programmed when a test of an internal circuit is passed. A mode setting circuit switches an operation mode to a normal operation mode or a test mode by exter... | 04/13/2010 |
| 7693675 | Method for protection of sensor node's data, a systems for secure transportation of a sensor node and a sensor node that achieves these Methods of confidential data sharing and mutual authentication between a sensor node and a router are established, and data in the sensor node is protected from a physical attack. Sensor node issuing processing is performed on a sensor node having a tamper resistant... | 04/06/2010 |
| 7689377 | Technique for aging induced performance drift compensation in an integrated circuit An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance. In one example embodiment, this is achieved by applying a body bias voltage VBB to the integrated circuit to com... | 03/30/2010 |
| 7684949 | Apparatus and method for determining reliability of an integrated circuit In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if... | 03/23/2010 |
| 7672803 | Input of test conditions and output generation for built-in self test A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adj... | 03/02/2010 |
| 7668682 | Method and circuit for detecting and compensating for a degradation of a semiconductor device A design structure and method comprising a degradation detection circuit configured to respond to degradation. The degradation detection circuit is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, a calculation ... | 02/23/2010 |
| 7660691 | Clock circuits and counting values in integrated circuits A clock circuit for an integrated circuit having at least one MOS transistor. The clock circuit includes a first circuit for inducing a degradation of the transistor as a function of time and circuit for measuring a parameter of the transistor that reflects a loweri... | 02/09/2010 |
| 7634376 | Internal bias measure with onboard ADC for electronic devices An apparatus and method for on-chip bias measurement of an analog signals on an integrated circuit with a switchable analog-to-digital converter capable of performing testing and other types of processing. Analog signal test locations are selected for testing by a t... | 12/15/2009 |
| 7630852 | Method of evaluating integrated circuit system performance using orthogonal polynomials A method for analyzing IC system performance. The method includes receiving system variables that correspond to an IC system; normalizing the system variables; using an infinite dimensional Hilbert space, modeling a system response as a series of series of orthogona... | 12/08/2009 |
| 7630851 | Estimation of average-case activity for circuit elements in a digital circuit A method for estimating the average-case activity in a digital circuit includes the steps of identifying one or more predesignated types of circuit elements in the digital circuit, and propagating activity values through any identified circuit elements using a prede... | 12/08/2009 |
| 7630853 | Non-linear junction based electronics detection Line anomalies on a line under test are detected by generating a test signal at a first power level and coupling the test signal to the line under test. A response level is received from the line under test at a second and third harmonic frequency of the first test ... | 12/08/2009 |
| 7627445 | Apparatus for testing a device with a high frequency signal The present invention provides an apparatus for testing a device with a high frequency signal, such as an RF signal. The apparatus delivers a high frequency signal directly to a loadboard with a coaxial cable. The coaxial cable can deliver the signal to a location a... | 12/01/2009 |
| 7623982 | Method of testing an electronic circuit and apparatus thereof A method of testing an electronic circuit is provided. The method comprises radiating a laser beam onto the electronic circuit, and determining a plurality of samples of a response signal output by the electronic circuit during the period when the laser beam is radi... | 11/24/2009 |
| 7617065 | Methodology for estimating statistical distribution characteristics of physical parameters of semiconductor device A method for estimating statistical distribution characteristics of physical parameters of a semiconductor device includes manufacturing a plurality of semiconductor device chips, each having a plurality of transistors, preparing electrical characteristic data by me... | 11/10/2009 |
| 7617064 | Self-test circuit for high-definition multimedia interface integrated circuits A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high ... | 11/10/2009 |
| 7617066 | Virtual crimp validation system A system for validating a proposed crimp includes a pre-crimp modeler configured to establish a geometry for the proposed crimp, a plurality of virtual testing modules configured to determine at least one characteristic of the proposed crimp, and a virtual validatio... | 11/10/2009 |
| 7606677 | Dynamic measurement control A metrology recipe includes dynamic instructions that allow a metrology tool to perform a secondary metrology operation on a test wafer when previous measurement data indicates a process issue with that test wafer. The metrology recipe can instruct the metrology too... | 10/20/2009 |
| 7590503 | Method and system for rerouteable cyclic redundancy check sum (CRC) for different sources Provided is a system and method including a number of routers structured and arranged to route one or more video sources to any of one or more destinations. Each of the number of routers including a plurality of input and output ports and each input port being conne... | 09/15/2009 |
| 7587294 | SATA device having self-test function for OOB-signaling Disclosed is a SATA device having self-testing function with an OOB-signaling operation and a method of testing the same. The SATA device includes target and test-signaling controllers that sequentially generate and transceive control signals for the OOB-signaling o... | 09/08/2009 |
| 7580806 | Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the a... | 08/25/2009 |
| 7580807 | Test protocol manager for massive multi-site test Disclosed herein is a massive multi-site (MMS) testing architecture. The MMS architecture includes a MMS interface on each of a plurality of devices under test. The MMS interface includes a test protocol manager that may receive test stimulus and send the test stimu... | 08/25/2009 |
| 7574319 | Instrument architecture with circular processing queue Apparatuses for a test and measurement instrument provide an instrument capable of handling acquisition, transfer, analysis, and display of large quantities of waveform data and complex waveforms. The apparatus for a test and measurement instrument consists of multi... | 08/11/2009 |
| 7571067 | Instrument ring architecture for use with a multi-core processor Apparatuses for a test and measurement instrument provide an instrument capable of handling acquisition, transfer, analysis, and display of large quantities of waveform data and complex waveforms. The apparatus for a test and measurement instrument consists of multi... | 08/04/2009 |
| 7567882 | Method for evaluating semiconductor device The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed... | 07/28/2009 |
| 7565256 | Displacement detecting encoder A displacement detecting encoder including a scale having a positional code that contains positional information, a detection portion which is disposed so as to make a relative movement with respect to the scale and detect at least a part of the positional code equi... | 07/21/2009 |
| 7561980 | Transmission medium testing apparatus and method The invention provides a method for testing a transmission medium used in a full-duplex communication system comprising an endpoint that comprises a transmitting end (TX) and a receiving end (RX); the method comprises the steps of: first, transmitting a transmitted ... | 07/14/2009 |
| 7552024 | Circuit board diagnostic operating center A circuit board diagnostic operating center (10) including a large flat panel display (18) used for displaying the test system assets (instruments 12) and the circuit card assembly (CCA) schematic diagram, a small flat panel display (20) ... | 06/23/2009 |
| 7539589 | Testing radio frequency and analogue circuits A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped up (step 100) and quiescent current measurements are taken at selected values of VDD (step 102) to generate a current signature (step 104). When ... | 05/26/2009 |
| 7539590 | System and method for testing a memory A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and ... | 05/26/2009 |
