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| Number | Title | Issue Date |
| 7136519 | Specimen topography reconstruction This method removes high frequency noise from shape data, significantly improves metrology system (10) performance and provides very compact representation of the shape. This model-based method for wafer shape reconstruction from data measured by a dimensiona... | 11/14/2006 |
| 7137083 | Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure A method and apparatus for verifying an integrated circuit device test for testing an integrated circuit device on an automated tester is presented. An integrated circuit device simulator simulates a flawed integrated circuit device that models one or more known fla... | 11/14/2006 |
| 7136958 | Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors ... | 11/14/2006 |
| 7136770 | Using component-level calibration data to reduce system-level test Using component-level test data to reduce system test. By modeling a system, sensitivity analysis reveals critical components and parameters of those components required to meet system performance parameters. Critical components are tested for these parameters, and ... | 11/14/2006 |
| 7136771 | Semiconductor device and testing circuit which can carries out a verifying test effectively for non-volatile memory cells A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. Th... | 11/14/2006 |
| 7133991 | Method and system for capturing and bypassing memory transactions in a hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock sign... | 11/07/2006 |
| 7132761 | Universal fleet electrical system The universal fleet electrical system is an integrated system for supplying electrical power to aftermarket accessories, particularly to police vehicles and other emergency vehicles. The system includes a central power distribution panel, which includes a fuse panel... | 11/07/2006 |
| 7133799 | Printhead assembly with composite support beam for a pagewidth printhead A pagewidth printhead assembly that includes a support beam assembly having a composite shell of metals selected so that the shell has a coefficient of thermal expansion substantially the same as that of silicon and a core located within the shell and defining a num... | 11/07/2006 |
| 7133797 | Method, apparatus, system, program and medium for inspecting a circuit board and an apparatus incorporating the circuit board A method, apparatus, system, computer program and medium, for inspecting a wide variety of circuit boards. A controller generates test data and reference data according to characteristic information of a circuit board. Using the test data, the circuit board generate... | 11/07/2006 |
| 7133818 | Method and apparatus for accelerated post-silicon testing and random number generation A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the ... | 11/07/2006 |
| 7133798 | Monitoring signals between two integrated circuit devices within a single package In one embodiment, a method is provided for monitoring signals communicated between a first integrated circuit chip and a second integrated circuit chip within a single packaged semiconductor device, wherein at least some external terminals for the packaged semicond... | 11/07/2006 |
| 7130233 | Sensing circuit for single bit-line semiconductor memory device A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electricall... | 10/31/2006 |
| 7127652 | X-tree test method and apparatus in a multiplexed digital system An X-Tree test apparatus for testing combinatorial logic circuits in a multiplexed digital system. The apparatus includes a plurality of contacts for electrical connection with pins on a device under test. A first driver drives a logic one signal, and a second drive... | 10/24/2006 |
| 7126346 | Method, apparatus, and article of manufacture for manufacturing high frequency balanced circuits A method, apparatus and article of manufacture for manufacturing a balanced circuit obtains S-parameters for the balanced circuit and determines a delay value embedded at one of the single-ended terminals of the balanced circuit that reduces a differential to common... | 10/24/2006 |
| 7120551 | Method for estimating EMI in a semiconductor device The resistance value of a supply line (Rline), the resistance value of a decoupling capacitor (Rcap), and the resistance value of a transistor (Rmos) are separately calculated from mask layout information of a semiconductor integrated circuit. The resistance value b... | 10/10/2006 |
| 7120511 | Method and system for scheduling maintenance procedures based upon workload distribution The present invention is generally directed to various methods and systems for scheduling maintenance procedures based upon workload distribution. In one illustrative embodiment, the method includes providing a tool, identifying a planned processing schedule for pro... | 10/10/2006 |
| 7119549 | Output calibrator with dynamic precision An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver... | 10/10/2006 |
| 7120743 | Arbitration system and method for memory responses in a hub-based memory system A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to the bypass path that stores downstream memory responses from the bypass path. A multiplexer is coupled to t... | 10/10/2006 |
| 7116125 | Semiconductor test device using leakage current and compensation system of leakage current The present invention relates to a semiconductor test device which may use a leakage current and/or a compensation system of leakage current. The semiconductor test device, according to exemplary embodiments of the present invention, may include MOS transistors whic... | 10/03/2006 |
| 7117112 | Method and system for the interactive testing of assembled wireless communication devices A method for testing wireless communication devices in stages in a production line for the assembly of said devices, comprises assembling each respective wireless communication device such that each device includes an interactive test component for interactively tes... | 10/03/2006 |
| 7117405 | Extender card with intercepting EEPROM for testing and programming un-programmed memory modules on a PC motherboard An extender card is plugged into a memory module socket on a personal computer (PC) motherboard. The extender card has a test socket that receives a memory module under test. The extender card has an intercepting EEPROM chip that receives device-select lines from th... | 10/03/2006 |
| 7114087 | Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), a bus coupled to the CPU and a chipset coupled to the bus. The chipset includes compensation circuitry to compensate for process, voltage and tem... | 09/26/2006 |
| 7112982 | Method for evaluating semiconductor device It is an object of the present invention to provide a method for evaluating a semiconductor device including a semiconductor, an insulator, and a conductor. The present invention has a first step of applying a voltage to a conductor to measure a current value... | 09/26/2006 |
| 7113881 | Method and apparatus for semi-automatic extraction and monitoring of diode ideality in a manufacturing environment A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by h... | 09/26/2006 |
| 7113880 | Video testing via pixel comparison to known image Methods and systems provide automated testing of computer-generated displays. The proper functionality of a memory storage device on a computer video card and the proper functionality of software for generating computer-generated displays may be tested by storing a ... | 09/26/2006 |
| 7110905 | Universal automated circuit board tester An apparatus and method for automatically testing circuit boards, such as computer system boards and the like. The circuit board device under test (DUT) is loaded into an automated test apparatus (tester), which includes a mechanism for automatically connecting test... | 09/19/2006 |
| 7111198 | Multithread auto test method A multithread auto test method is disclosed for the test process of computer hardware. According to the exclusion relation among the unique IDs of the test items, a multithread executable logic is automatically generated. An appropriate parallel method is employed t... | 09/19/2006 |
| 7109738 | Method for modeling inductive effects on circuit performance A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a device under test (DUT) and three reference oscillators overlying a substrate of the wafer; measuring the frequencies of the reference oscillators as influe... | 09/19/2006 |
| 7109734 | Characterizing circuit performance by separating device and interconnect impact on signal delay An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconn... | 09/19/2006 |
| 7109902 | Method and system for sampling a signal According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal generated using a first clock signal by a first device. The method also includes sampling the analog signal usi... | 09/19/2006 |
| 7110932 | Method and circuit arrangement for regulating the operating voltage of a digital circuit A method and circuit arrangement for determining performance of a digital circuit to a critical degree by the transit time of signals of the longest signal path, also called the critical path. Since the signal transit time is influenced by the operating voltage, by ... | 09/19/2006 |
| 7107171 | Production procedure with PCB calibration A method for testing an optical disc drive control PCB using a test jig featuring a reference optical pick-up head. The method includes steps for measuring an output of the reference optical pick-up head (OPU) laser, comparison of the OPU output to the output of an ... | 09/12/2006 |
| 7107172 | Test apparatus and setting method therefor A test apparatus for testing an electric device includes a plurality of signal input-output units for inputting and/or outputting test signals in response to each of a plurality of terminals included by the electric device, a channel selection memory for storing pie... | 09/12/2006 |
| 7107557 | Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit In a circuit simulation step, a cell transistor level net list is input, the slew of an input signal waveform and the magnitude of a load capacitance connected to a cell output terminal are varied for each cell, to perform a circuit simulation of each cell for obtai... | 09/12/2006 |
| 7107493 | System and method for testing for memory errors in a computer system The specification may disclose a computer system that may operate a portion of available memory as backup to a primary memory, and the computer system may be adapted to test the backup memory for memory errors at times other than execution of power-on self-test proc... | 09/12/2006 |
| 7107515 | Radiation hard divider via single bit correction A radiation hard logic device such as a divider is disclosed. The logic device includes a voter module to determine an error free logic device output, a feedback module to generate a correction signal and provide the signal to a logic correction module to correct th... | 09/12/2006 |
| 7102357 | Determination of worst case voltage in a power supply loop Various systems, methods, and programs embodied in a computer readable medium are provided for determining a worst-case impedance and worst-case voltage of a power supply loop coupled to a power input of a die. In various embodiments, the worst-case impedance of a p... | 09/05/2006 |
| 7102377 | Packaging reliability superchips A test chip module for testing the integrity of the flip chip solder ball interconnections between chip and substrate. The interconnections are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ub... | 09/05/2006 |
| 7103493 | Memory testing apparatus and method Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector,... | 09/05/2006 |
| 7103488 | Method for determining fringing capacitances on passive devices within an integrated circuit A method for detemiining fringing capacitances on passive devices within an integrated circuit is disclosed. A fringing capacitance region on a passive device is initially divided into a group of fringing electric field areas. A set of fringing capacitance equations... | 09/05/2006 |
