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| Number | Title | Issue Date |
| 7315999 | Method and apparatus for identifying assist feature placement problems One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems due to a missing or an improperly placed assist feature. During operation, the system receives an uncorrected or correc... | 01/01/2008 |
| 7312865 | Method for in situ monitoring of chamber peeling A method for in situ monitoring of particles generated by a reaction by-product film peeling from an interior wall of a reaction chamber of a semiconductor fabrication apparatus to determine reaction chamber condition. The method includes the steps of: exciting the ... | 12/25/2007 |
| 7313452 | Substrate transfer controlling apparatus and substrate transferring method A substrate transfer controlling apparatus can easily maximize throughput of a substrate processing apparatus such as a semiconductor fabrication apparatus, and can satisfy a demand for immediacy of actions of a transfer device. The substrate transfer controlling ap... | 12/25/2007 |
| 7312848 | Positioning apparatus, exposure apparatus, and device manufacturing method This invention discloses an apparatus having a base and a movable body which is driven to move along the base. The apparatus includes a generator configured to generate a driving signal for the movable body, a temperature adjusting mechanism configured to adjust tem... | 12/25/2007 |
| 7313456 | Method and apparatus for capturing and using design intent in an integrated circuit fabrication process A method and apparatus for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufact... | 12/25/2007 |
| 7313508 | Process window compliant corrections of design layout The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the ... | 12/25/2007 |
| 7313450 | Automatic methods and systems for manufacturing recipe feedback control Automatic methods and systems for manufacturing recipes feedback control. Relationships among manufacturing recipes are determined. Wafers are processed based on the manufacturing recipes. The wafers are measured by metrology tools after processing. Feedback informa... | 12/25/2007 |
| 7310563 | Fabrication system and fabrication method A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses ... | 12/18/2007 |
| 7308395 | Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group According to an aspect of the present invention, there is provided a simulation circuit pattern evaluation method including: designing an aggregate of simulation circuit patterns, which simulate a circuit pattern of a semiconductor integrated circuit, by combining p... | 12/11/2007 |
| 7305278 | Enterprise factory control method and system A system, method, service and media for managing both supplier-owned and non-owned manufacturing asset types utilizing a supplier model of a product which goes across the manufacturing asset types. The invention maps the model to instances of the asset types and use... | 12/04/2007 |
| 7305320 | Metrology tool recipe validator using best known methods A method of preparing recipes for operating a metrology tool, each recipe including a set of instructions for measuring dimensions in a microelectronic feature. A database includes a plurality of known instructions with best known methods for measuring different fea... | 12/04/2007 |
| 7305276 | Method, system, and computer program product for controlling the flow of material in a manufacturing facility using an extended zone of control The present invention provides a method, system, and computer program product for controlling the flow of material in a manufacturing facility using an extended zone of control. A method in accordance to an embodiment of the present invention comprises establishing ... | 12/04/2007 |
| 7305651 | Mask CD correction based on global pattern density The present disclosure provides a method of forming a photomask layout. In one example, the method comprises selecting a pattern feature on the photomask layout, defining a global area centered at the pattern feature on the photomask layout, calculating a pattern de... | 12/04/2007 |
| 7303982 | Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpi... | 12/04/2007 |
| 7305334 | Methodology for image fidelity verification A method for predicting functionality of an integrated circuit segment to be lithographically printed on a wafer. Initially there is provided a two-dimensional design of an integrated circuit, including an integrated circuit segment having critical width, and a two-... | 12/04/2007 |
| 7304485 | Analysis of the quality of contacts and vias in multi-metal fabrication processes of semiconductor devices, method and test chip architecture A test chip performs measurements to evaluate the performances of interconnects. In particular, the statistical failure distribution, the electromigration and the leakage current are measured. An algorithm detects a via failure at any of the available n metal layers... | 12/04/2007 |
| 7305642 | Method of tiling analog circuits The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. ... | 12/04/2007 |
| 7305634 | Method to selectively identify at risk die based on location within the reticle A method and system of selectively identifying at risk die based on location within the reticle. Reticle and stepping information is stored in a database. All reticle shots in a wafer and in a lot are overlaid on top of each other. The reticle and stepping informati... | 12/04/2007 |
| 7304001 | Fabrication methods of semiconductor integrated circuit device and photomask Under the condition that a semiconductor maker and a photomask maker are separated but these are mutually connected with a communication line, the semiconductor maker gives a photomask fabrication schedule information to the photomask maker via the communication lin... | 12/04/2007 |
| 7302304 | Systems and methods for production planning A system for production planning. A MES provides production information corresponding to a preset time period of a production line, monitors processing of work-in-process (WIP), and provides processing status information of the WIP. A processor determines a move tar... | 11/27/2007 |
| 7302305 | Job queue management system and method thereof, including clustering wafer lots processed by common recipe into group, and creating process job and control job A system and method for job queue management. A job queue management apparatus acquires multiple wafer lot records individually regarding a plurality of wafers processed by a recipe, clusters the wafer lots by the common recipe into a group, creates a process job co... | 11/27/2007 |
| 7302307 | Micrologistics tracking system and method for an automated manufacturing facility A method of monitoring activity in an automated fabrication facility in which work-in-process material lots undergo manufacturing operations and storage operations includes tracking processing load and unload times of the lots at each of the manufacturing operations... | 11/27/2007 |
| 7299105 | Method and system for controlling a product parameter of a circuit element Methods and systems are disclosed that allow an adjustment of a product parameter, such as operating speed, of a circuit element, such as a field effect transistor, during the fabrication of the device. A manufacturing process downstream of a first controlled proces... | 11/20/2007 |
| 7299203 | Method for storing and shipping programmable ASSP devices A novel method for order processing, manufacturing and distributing integrated circuits (ICs) including the steps of: dry packing a plurality of programmable ICs and placing the dry packed programmable ICs into inventory such that the inventory is re-accessible in a... | 11/20/2007 |
| 7299104 | Substrate processing apparatus and substrate transferring method Shock waves occurring when opening a gate valve between two vacuum chambers and peeling of particles by a viscous force taking place when a gas is supplied into a vacuum chamber are necessary to be suppressed by the apparatus and method of the invention, whereby con... | 11/20/2007 |
| 7299106 | Method and apparatus for scheduling metrology based on a jeopardy count The present invention provides a method that includes determining a jeopardy count associated with at least one processing tool and selecting at least one wafer based upon the jeopardy count, the at least one wafer having been processed by the at least one processin... | 11/20/2007 |
| 7299107 | Method for analyzing effective polishing frequency and effective polishing times for chemical mechanical planarization polishing wafers with different polishing pad profiles A method for analyzing polishing frequency and number of polishing times for chemical planarization polishing wafer with different polishing pad profiles is disclosed. First, drawings of a wafer and a polishing pad are provided and then are converted into pixel arra... | 11/20/2007 |
| 7295954 | Expert knowledge methods and systems for data analysis A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one... | 11/13/2007 |
| 7294039 | Polishing system with in-line and in-situ metrology A computer-implemented method for process control in chemical mechanical polishing in which an initial pre-polishing thickness of a substrate is measured at a metrology station, a parameter of an endpoint algorithm is determined from the initial thickness of the sub... | 11/13/2007 |
| 7295885 | Multi-exposure drawing method and apparatus thereof for dividing an exposing area into exposed zones and un-exposed zones based on odd-numbered and even-numbered vector-graphic data In a drawing method, all information on a pattern to be drawn on a drawing surface, represented by first vector-graphic data of a drawing-coordinate-system, is transmitted to an exposure drawing apparatus having a plurality of optical modulation elements. The first ... | 11/13/2007 |
| 7296103 | Method and system for dynamically selecting wafer lots for metrology processing The present invention is generally directed to various methods and systems for dynamically controlling metrology work in progress. In one illustrative embodiment, the method comprises providing a metrology control unit that is adapted to control metrology work flow ... | 11/13/2007 |
| 7294906 | Wiring technique An apparatus for supplying electrical power to a movable member. The apparatus includes a fixed member, the movable member moving relative to the fixed member, a flexible wiring member having an end connected to the movable member and another end connected to the fi... | 11/13/2007 |
| 7294440 | Method to selectively correct critical dimension errors in the semiconductor industry A method to correct critical dimension errors during a semiconductor manufacturing process. The method includes providing a first semiconductor device. The first semiconductor device is analyzed to determine at least one critical dimension error within the first sem... | 11/13/2007 |
| 7292905 | Method and system for identifying manufacturing anomalies in a manufacturing system A method and system for identifying manufacturing anomalies in a manufacturing system comprising a plurality of products which are manufactured with a plurality of manufacturing parameters is disclosed. The system comprises a data mining program applied to the data ... | 11/06/2007 |
| 7292959 | Total tool control for semiconductor manufacturing The present invention provides a method and apparatus for controlling processing tools and related control units. The method includes accessing information indicative of at least one excursion of at least one processing tool detected by a first control unit associat... | 11/06/2007 |
| 7292906 | Formula-based run-to-run control A processing method of processing a substrate is presented that includes: receiving pre-process data, wherein the pre-process data comprises a desired process result and actual measured data for the substrate; determining a required process result, wherein the requi... | 11/06/2007 |
| 7292058 | Method for estimating the early failure rate of semiconductor devices According to one embodiment of the invention, a method for estimating the failure rate of semiconductor devices includes obtaining accelerated stress duration data for a plurality of semiconductor devices, determining which of the semiconductor devices fail, classif... | 11/06/2007 |
| 7292426 | Substrate holding system and exposure apparatus using the same A substrate holding system having a chuck for vacuum attraction and electrostatic attraction of a substrate. The system includes a ring-like rim for carrying a substrate thereon, a plurality of first protrusions disposed inside the rim, for carrying the substrate th... | 11/06/2007 |
| 7292046 | Simulated module load A circuit and method of operation for simulating a capacitive load for an integrated circuit or chip. The circuit adds a small capacitor to a test cell that tests the performance of a chip, such as a DRAM memory device, so that it may be tested realistically before ... | 11/06/2007 |
| 7291285 | Method and system for line-dimension control of an etch process A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the ... | 11/06/2007 |
