Class 505/473 - Vapor deposition

Subclass of Class 505 - Superconductor technology: apparatus, material, process
Definition: Process wherein a material in a gaseous state (e.g., vapor,
No. of patents: 211
Last issue date: 11/24/2009

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Number	Title	Issue Date
7622426	Methods of controlling hydrogen fluoride pressure during chemical fabrication processes The present invention is a method for producing a crystalline end-product. The method comprising exposing a fluoride-containing precursor to a hydrogen fluoride absorber under conditions suitable for the conversion of the precursor into the crystalline end-product.	11/24/2009
7431868	Method of manufacturing a metal substrate for an oxide superconducting wire A metal substrate for an oxide superconducting wire, which comprises a polycrystalline metal substrate with a rolled aggregate structure having a {100} plane which is parallel to the rolled surface and a axis which is parallel to the rolling direction, and an ...	10/07/2008
7387811	Method for manufacturing high temperature superconducting conductors using chemical vapor deposition (CVD) A CVD apparatus capable of substantially simultaneously processing multiple portions of at least one substrate or substantially simultaneously processing portions of multiple substrates or substantially simultaneously processing multiple portions of at least one sub...	06/17/2008
7371586	Superconductor and process for producing the same A superconductor and a method for producing the same are provided. The method for producing a superconductor includes the step of forming a superconducting layer on a base layer by performing a film deposition at least three times, wherein the film thickness of a su...	05/13/2008
7361377	Fluorinated precursors of superconducting ceramics, and methods of making the same This invention provides a method of making a fluorinated precursor of a superconducting ceramic. The method comprises providing a solution comprising a rare earth salt, an alkaline earth metal salt and a copper salt; spraying the solution onto a substrate to provide...	04/22/2008
7339182	Vacuum evaporator A vacuum evaporator including a vacuum chamber and a source arranged in the vacuum chamber to supply a deposition material to a substrate on which a layer is formed. A crystal sensor measures a deposition speed of the deposition material. The crystal sensor includes...	03/04/2008
7338683	Superconductor fabrication processes A method of forming a superconductive device is provided, including providing a substrate having a dimension ratio of not less than about 102, depositing a buffer film to overlie the substrate by ion beam assisted deposition utilizing and ion beam, monito...	03/04/2008
7294606	Substrate and method for the formation of continuous magnesium diboride and doped magnesium diboride wire A chemically doped boron coating is applied by chemical vapor deposition to a silicon carbide fiber and the coated fiber then is exposed to magnesium vapor to convert the doped boron to doped magnesium diboride and a resultant superconductor. ...	11/13/2007
7276456	Article comprising an oxide layer on a GaAs-based semiconductor structure and method of forming same A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor s...	10/02/2007
7247340	Method of making a superconducting conductor A method of forming a superconducting conductor is disclosed. The method provides translating a substrate tape through a deposition chamber and along a helical path, where the helical path has multiple windings of the substrate tape and each winding of the substrate...	07/24/2007
7221586	Memory utilizing oxide nanolaminates Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region b...	05/22/2007
7208196	Epitaxial oxide films via nitride conversion The present invention relates to oxides on suitable substrates, as converted from nitride precursors. ...	04/24/2007
7208804	Crystalline or amorphous medium-K gate oxides, Y0and Gd0 A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxi...	04/24/2007
7205620	Highly reliable amorphous high-k gate dielectric ZrON A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate dielectrics formed from metals such as zirconium are thermodynamically...	04/17/2007
7187587	Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou...	03/06/2007
7166886	DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage...	01/23/2007
7135734	Graded composition metal oxide tunnel barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The float...	11/14/2006
7132711	Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h...	11/07/2006
7126183	Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which h...	10/24/2006
7112841	Graded composition metal oxide tunnel barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The float...	09/26/2006
7090889	Boride thin films on silicon Boride thin films of conducting and superconducting materials are formed on silicon by a process which combines physical vapor deposition with chemical vapor deposition. Embodiments include forming boride films, such as magnesium diboride, on silicon substrates by p...	08/15/2006
7087954	In service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu...	08/08/2006
7087113	Textured substrate tape and devices thereof A method for forming a sharply biaxially textured substrate, such as a single crystal substrate, includes the steps of providing a deformed metal substrate, followed by heating above the secondary recrystallization temperature of the deformed substrate, and controll...	08/08/2006
7074744	Apparatus for consecutive deposition of high-temperature superconducting (HTS) buffer layers A method of coating a substrate for a high temperature superconductor material is disclosed, including loading a substrate into a first deposition chamber, routing the substrate in the first deposition chamber such that the substrate forms a helical winding in the f...	07/11/2006
7075829	Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou...	07/11/2006
7074673	Service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu...	07/11/2006
7045430	Atomic layer-deposited LaAlO3 films for gate dielectrics A dielectric film containing LaAlO3 and method of fabricating a dielectric film contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate di...	05/16/2006
7046719	Soft handoff between cellular systems employing different encoding rates A receiver (200) is provided receiving signals from differing base stations (BTSA and BTSB). The signal from BTSA is encoded using a first rate convolutional encoder while the signal transmitted from BTSB is encoded...	05/16/2006
7042043	Programmable array logic or memory devices with asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain ...	05/09/2006
7025855	Insulation-film etching system This application discloses an insulation-film etching system that etches an insulator film on a substrate by a species produced in plasma. The apparatus comprises a process chamber in which the etching process is carried out, a substrate holder that is provided in t...	04/11/2006
7027328	Integrated circuit memory device and method Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the ch...	04/11/2006
6995507	Method for depositing thin film for element, and organic electroluminescence element The present invention concerns a method of forming one or more thin films on a substrate by depositing two or more materials by vacuum evaporation, comprising, depositing each material under such control that ni value of the each material is k±0.5 wherein k is a co...	02/07/2006
6974501	Multi-layer articles and methods of making same The invention relates to multi-layer articles and methods of making such articles. The methods include first conditioning the surface of an underlying layer, such as a buffer layer or a superconductor layer, then disposing a layer of material on the conditioned surf...	12/13/2005
6963103	SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide the SRAM cell with a definitive asymmetry so that the cell always start...	11/08/2005
6958937	DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floatin...	10/25/2005
6953730	Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable s...	10/11/2005
6952032	Programmable array logic or memory devices with asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain ...	10/04/2005
6950340	Asymmetric band-gap engineered nonvolatile memory device Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a sub...	09/27/2005
6933065	High temperature superconducting thick films An article including a substrate, a layer of an inert oxide material upon the surface of the substrate, (generally the inert oxide material layer has a smooth surface, i.e., a RMS roughness of less than about 2 nm), a layer of an amorphous oxide or oxynitride materi...	08/23/2005
6929820	Method of forming a superconductor film A method includes forming an as-grown film of a superconductor composed of a MgB2 compound which is made by simultaneous evaporation of magnesium and boron. The as-grown film is superconductive without an annealing process to make the film superconductive...	08/16/2005

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Class 505/473 - Vapor deposition