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| Number | Title | Issue Date |
| 8175563 | Programmable baseband filters supporting auto-calibration for a mobile digital cellular television environment A method for processing wireless information is disclosed and may include performing by one or more circuits within a single-chip multi-band RF receiver, the one or more circuits comprising a filter, generating at least one control signal based on a signal strength ... | 05/08/2012 |
| 8170518 | Dual antenna system having one phase lock loop Circuits, systems, and methods are disclosed for controlling multiple antenna receive paths in a wireless communication device. In some embodiments, the circuit may include a pair of receiving antennas, a first receive path including a VCO coupled to receive a PLL s... | 05/01/2012 |
| 8145171 | Clock clean-up phase-locked loop (PLL) A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated... | 03/27/2012 |
| 8140039 | Quadrature-input quadrature-output divider and phase locked loop frequency synthesizer or single side band mixer The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divide... | 03/20/2012 |
| 8140040 | Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated circuit An integrated circuit including a Phase Locked Loop (PLL) configured for use with a continuous stream receiver is disclosed. A control voltage line is configured to deliver a control voltage with a capacitive load delivered by a capacitor array to the control voltag... | 03/20/2012 |
| 8131243 | Receiving circuit and timepiece In a receiving circuit 44 for receiving an electromagnetic wave signal, a frequency converter/detector circuit 100 comprises a local oscillator 131 for generating an oscillation signal, plural mixers 133, 134 for mixing the received elect... | 03/06/2012 |
| 8121573 | Method and system for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a freq... | 02/21/2012 |
| 8112054 | Tri-stating a phase locked loop to conserve power In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a de... | 02/07/2012 |
| 8090335 | Method and apparatus for an adaptive step frequency calibration An open loop frequency calibration algorithm is employed whereby frequency counters are utilized to provide frequency information concerning the difference in frequency between a local oscillator and a reference signal prior to obtaining phase locked operation of a ... | 01/03/2012 |
| 8073416 | Method and apparatus for controlling a bias current of a VCO in a phase-locked loop A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO... | 12/06/2011 |
| 8060046 | Radio receiver and radio reception method The radio receiver includes: a mixer configured to convert a received signal to an IF signal using a local oscillation signal; an IF processing section configured to limit the band of the IF signal; a detection section configured to demodulate the band-limited IF si... | 11/15/2011 |
| 8019301 | Calibration techniques for frequency synthesizers In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase lo... | 09/13/2011 |
| 8010072 | Charge pump current compensation for phase-locked loop frequency synthesizer systems A technique for improving frequency synthesizer performance by frequency-compensating charge pump current in order to maintain a consistent loop bandwidth over a wide operating frequency range is described. A relationship between the capacitance value associated wit... | 08/30/2011 |
| 7953383 | Dual band receiver There is provided a dual band receiver receiving frequency signals in different bands, the receiver including: a first down converter converting a first band signal into a first intermediate frequency signal; a second down converter converting a second band signal i... | 05/31/2011 |
| 7904045 | Phase detector comprising a switch configured to select a phase offset closest to a phase of an amplifier A phase detector includes a plurality of phase detectors located in a phase correction loop, each phase detector configured to receive as input a radio frequency (RF) input signal and an RF reference signal, each of the plurality of phase detectors also configured t... | 03/08/2011 |
| 7899424 | Transmitter power amplifier ramping method A method for reducing frequency glitches in a digital transceiver due to power amplifier input impedance variations. According to the method, the power amplifier is switched on after the end of a prior packet reception period and before a new packet transmission beg... | 03/01/2011 |
| 7869782 | Multi-mode transmit and receive PLL A local oscillator (LO) signal generator that has a reference phase-locked loop (PLL), a receiver LO PLL and a transmitter LO PLL. A reference PLL is coupled to receive a reference clock input and to generate a reference PLL signal at its output, which then drives a... | 01/11/2011 |
| 7848725 | RF transmitter with stable on-chip PLL A phase locked loop (PLL) a phase detector, a charge pump, a loop filter, a controlled oscillator, and a feedback divider. The phase detector is coupled to produce a difference signal based on a difference between phase of a reference oscillation and phase of a feed... | 12/07/2010 |
| 7840202 | Method and system for compensation of DC offset in an RF receiver System and method for processing signals are disclosed. The method may include converting, in an RF receiver, one or more analog samples, which are selected from one of a plurality of output paths of the RF receiver, to one or more digital samples. A digital feedbac... | 11/23/2010 |
| 7817977 | Configurable signal generator A method of generating an output signal comprises receiving an input signal, mixing the input signal with a reference signal having a reference frequency to obtain an intermediate frequency signal having an intermediate frequency, filtering the intermediate frequenc... | 10/19/2010 |
| 7809345 | Digital PLL and applications thereof A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference b... | 10/05/2010 |
| 7805123 | RF transceiver using hopping frequency synthesizer A technique of frequency hopping communication capable of high-speed switching of a plurality of signals having ultra-wide band 528 MHz bandwidth at high-speed and setting and switching a band center frequency and the number of bands arbitrary is provided. A radio t... | 09/28/2010 |
| 7792509 | Transceiver with multi-state direct digital synthesizer driven phase locked loop Transceivers for use in time division telecommunication units in a transmitting mode, include switching a direct digital synthesizer (DDS) driven phase locked loop (PLL) into a modulating state and supplying a modulation signal to the DDS and switching in the PLL a ... | 09/07/2010 |
| 7792510 | Multi-band frequency synthesizer A multi-mode PLL frequency synthesizer of a wireless multi-mode transceiver is provided which includes a reference frequency source providing an oscillator signal with a constant reference frequency, a first frequency synthesizer subunit for converting the signal in... | 09/07/2010 |
| 7792511 | Security system with dynamic range enhancement for FM demodulation A system and method for communicating between a base and a remote device in a security system. The base receives an audio signal from a telephone network via a panel and then frequency modulates the audio signal at a carrier frequency to generate an FM signal. The r... | 09/07/2010 |
| 7778620 | Controlling phase locked loop in a mobile station A method of controlling a phase locked loop in a mobile station and a mobile station of a cellular telecommunications system are provided. The mobile station comprises an integrated phase locked loop for generating output frequencies; a frequency control unit for pr... | 08/17/2010 |
| 7747237 | High agility frequency synthesizer phase-locked loop A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more ... | 06/29/2010 |
| 7711340 | Phase locked loop and method thereof A phase locked loop and method thereof are provided. The example phase locked loop may include a loop filter filtering a charge pump output signal to generate a voltage signal and a voltage-controlled oscillator configured to operate in a given one of a plurality of... | 05/04/2010 |
| 7706767 | Dual path loop filter for phase lock loop A dual path loop filter circuit for a phase lock loop is described. The filter circuit allows the filter to be integrated into a phase lock loop IC circuit without using active circuit components that may create additional noise and consume additional power. The fil... | 04/27/2010 |
| 7697912 | Method to adjustably convert a first data signal having a first time domain to a second data signal having a second time domain The present invention provides a method to adjustably sample a first digitized signal having a first data rate to produce a second digitized signal having a second data rate. This involves processing the second digitized signal to produce an output signal having a t... | 04/13/2010 |
| 7689191 | Semiconductor integrated circuit having built-in PLL circuit A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits ... | 03/30/2010 |
| 7668524 | Clock deskewing method, apparatus, and system An integrated circuit includes clock deskew circuitry. The deskew circuitry includes a loop circuit to align an input clock signal with an output clock signal, and also aligns transmitted data with the output clock signal. ... | 02/23/2010 |
| 7664477 | Communications system using a low cost oscillator and related method thereof A communications system includes a first oscillator for producing a first clock signal; a second oscillator for producing a second clock signal; and a secondary circuit coupled to the first oscillator and the second oscillator for determining a second oscillation fr... | 02/16/2010 |
| 7647033 | Semiconductor integrated circuit device for communication A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-con... | 01/12/2010 |
| 7630698 | Fast switching, dual frequency phase locked loop A fast switching, dual frequency phase locked loop comprising dual phase/frequency detectors, dual charge pumps, a pair of loop filters, and a low leakage voltage controlled oscillator. Each phase/frequency detector and associated tuning ports of the voltage control... | 12/08/2009 |
| 7627299 | Signal processing device and method for operating a signal processing device A signal processing device implemented in a semiconductor body includes a frequency conversion device and a converter connected to the frequency conversion device. The conversion device is coupled by a terminal to a terminal on the surface of the semiconductor body.... | 12/01/2009 |
| 7613439 | Programmable baseband filters supporting auto-calibration for a mobile digital cellular television environment Methods and systems for programmable baseband filters supporting auto-calibration in a mobile digital cellular television environment are provided. Aspects of the method may include generating within a single-chip multi-band RF receiver, at least one control signal ... | 11/03/2009 |
| 7610030 | Wireless transmit-only apparatus and method A wireless transmit-only apparatus (20) has a controller (21) that responds to a user interface 25 by correlating specific user input with a corresponding characterizing transmission parameter(s) as is stored in a memory (35) and by selec... | 10/27/2009 |
| 7606545 | Portable radio terminal and AFC control method A portable radio terminal for realizing automatic frequency control (AFC) for automatically controlling the oscillation frequency of an oscillator includes a unit for intermittently performing AFC operation, and a unit for shortening an AFC operation stop period whe... | 10/20/2009 |
| 7606546 | Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagneti... | 10/20/2009 |
