Quotables
"Telephone, n. An invention of the devil which abrogates some of the advantages of making a disagreeable person keep his distance. "
Ambose Bierce
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7396696 | Method for manufacturing super bright light emitting diode of nanorod array having InGaN quantum well An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting ... | 07/08/2008 |
| 7327026 | Vacuum diode-type electronic heat pump device and electronic equipment having the same An electronic heat pump device has an emitter and a collector, stems supporting these components, a spacing retention member for keeping a spacing between the stems constant, and a sealing member for maintaining a vacuum between the stems. The emitter has a first se... | 02/05/2008 |
| 7323709 | Method for increasing efficiency of thermotunnel devices The present invention comprises a tunneling device in which the collector electrode is modified so that tunneling of higher energy electrons from the emitter electrode to the collector electrode is enhanced. In one embodiment, the collector electrode is contacted wi... | 01/29/2008 |
| 7303969 | Method of making interband tunneling diodes Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not ... | 12/04/2007 |
| 7170103 | Wafer with vertical diode structures A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the dio... | 01/30/2007 |
| 7122418 | Method of fabricating organic light emitting diode device A method of fabricating an organic electroluminescent device. A substrate comprising an organic electroluminescent unit thereon is provided. A passivation layer is formed on the substrate to cover the organic electroluminescent layer. An ion beam is provided to perf... | 10/17/2006 |
| 7075121 | Magnetic tunneling junction element having thin composite oxide film A tunneling junction element comprises: a substrate; a lower conductive layer formed on the substrate; a first oxide layer formed on the lower conductive layer and having a non-stoichiometric composition;a second oxide layer formed on the first oxide layer and havin... | 07/11/2006 |
| 7056761 | Avalanche diode with breakdown voltage controlled by gate length In an avalanche structure, different breakdown voltages are achieved by making use of a polygate and forming a highly doped p-n junction beneath the polygate, and adjusting the gate length and optionally the bias voltage of the gate. ... | 06/06/2006 |
| 6900099 | Flash memory cell and method for fabricating the same A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed ov... | 05/31/2005 |
| 6890827 | Method of fabricating a silicon on insulator transistor structure for imbedded DRAM To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin act... | 05/10/2005 |
| 6869855 | Method for making electrode pairs The present invention is a method for introducing a low work function material into a pair of matched electrodes. The method involves fabricating a composite of two electrodes and a low work function material, and treating the composite so that it splits to give a p... | 03/22/2005 |
| 6803598 | Si-based resonant interband tunneling diodes and method of making interband tunneling diodes Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not ... | 10/12/2004 |
| 6803269 | High performance varactor diodes A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region... | 10/12/2004 |
| 6784046 | Method of making vertical diode structures A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the d... | 08/31/2004 |
| 6740552 | Method of making vertical diode structures A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the d... | 05/25/2004 |
| 6734031 | Solid-state imaging device and manufacturing method for solid-state imaging device A solid-state imaging device, comprises: a semi-conductor substrate demarcating a two-dimensional surface; a multiplicity of photoelectric conversion units formed being arranged in a plurality of rows and columns on the semiconductor substrate; a planarizing insulat... | 05/11/2004 |
| 6699754 | Flash memory cell and method for fabricating the same A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is ... | 03/02/2004 |
| 6645820 | Polycrystalline silicon diode string for ESD protection of different power supply connections An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit... | 11/11/2003 |
| 6555440 | Process for fabricating a top side pitted diode device A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to th... | 04/29/2003 |
| 6552413 | Diode Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are for... | 04/22/2003 |
| 6541316 | Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed lase... | 04/01/2003 |
| 6518105 | High performance PD SOI tunneling-biased MOSFET A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made s... | 02/11/2003 |
| 6448161 | Silicon based vertical tunneling memory cell A method of forming a memory device from a single transistor and a single RTD structure is provided. The method comprises the steps of forming a silicon base, an oxide layer over the base and a top thin silicon layer over the oxide layer. The top silicon ... | 09/10/2002 |
| 6436785 | Method of manufacturing semiconductor device with a tunnel diode A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions (2, 3) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions (2A, 3A) of the semiconductor regions... | 08/20/2002 |
| 6417526 | Semiconductor device having a rectifying junction and method of manufacturing same The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller dop... | 07/09/2002 |
| 6294412 | Silicon based lateral tunneling memory cell An SRAM memory cell device is provide having a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 Å thick, allowing for increased... | 09/25/2001 |
| 6284557 | Optical sensor by using tunneling diode A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the i... | 09/04/2001 |
| 6268273 | Fabrication method of single electron tunneling device A method of fabricating a single electron tunneling (SET) device, the method including forming a source electrode and a drain electrode a predetermined distance apart from each other on an insulating substrate, forming a metal layer having a thickness on ... | 07/31/2001 |
| 6248621 | Method of growing high-quality crystalline silicon quantum wells for RTD structures A method of forming a crystalline silicon well over a perovskite barrier layer, preferably for use in formation of a resonant tunneling diode. A silicon substrate (1) is provided of predetermined crystallographic orientation. A layer of crystallographic p... | 06/19/2001 |
| 6204110 | Methods of forming an SRAM A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) ... | 03/20/2001 |
| 6194746 | Vertical diode structures with low series resistance A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The di... | 02/27/2001 |
| 6015738 | Method for fabricating transistorless, multistable current-mode memory cells and memory arrays A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedan... | 01/18/2000 |
| 5956568 | Methods of fabricating and contacting ultra-small semiconductor devices A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produce... | 09/21/1999 |
| 5913120 | Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of ... | 06/15/1999 |
| 5770497 | Method of manufacturing a novel static memory cell having a tunnel diode A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at le... | 06/23/1998 |
| 5672535 | Method of fabricating DRAM cell with self-aligned contact A structure and method are provided for reducing DRAM cell area by eliminating the contact-to-gate spacing requirement while increasing the capacitor area by designing the capacitor to extend inside the contact, without sacrificing the sidewall capacitanc... | 09/30/1997 |
| 5670385 | Method for fabricating an optical controlled resonant tunneling oscillator An optical controlled resonant tunneling oscillator utilizing variation of a resonant tunneling oscillator in accordance with a negative differential resistance, a series resistance and a static capacitance varied in response to the intensity of light whe... | 09/23/1997 |
| 5629215 | Method of fabricating and contacting ultra-small three terminal semiconductor devices Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconducto... | 05/13/1997 |
| 5616515 | Silicon oxide germanium resonant tunneling A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from german... | 04/01/1997 |
| 5563087 | Method of fabricating InAs/GaSb/AlSb material system SRAM An SRAM including first and second RITDs each formed with a heterostructure including a GaSb active layer sandwiched between AlSb barrier layers, which are sandwiched between InAs layers with each RITD having a contact connected to a first of the InAs lay... | 10/08/1996 |
