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| Number | Title | Issue Date |
| 7547648 | Fabricating nanoscale and atomic scale devices This invention concerns the fabrication of nanoscale and atomic scale devices. The method involves creating one or more registration markers. Using a SEM or optical microscope to form an image of the registration markers and the tip of a scanning tunnelling microsco... | 06/16/2009 |
| 7435536 | Method to align mask patterns Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pit... | 10/14/2008 |
| 7435609 | Manufacturing method for exposure mask, generating method for mask substrate information, mask substrate, exposure mask, manufacturing method for semiconductor device and server There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substr... | 10/14/2008 |
| 7419882 | Alignment mark and alignment method for the fabrication of trench-capacitor dram devices A small-size (w | 09/02/2008 |
| 7414787 | Phase contrast microscope for short wavelength radiation and imaging method A phase contrast x-ray microscope has a phase plate that is placed in proximity of and attached rigidly to the objective to form a composite optic. This enables easier initial and long-term maintenance of alignment of the microscope. In one example, they are fabrica... | 08/19/2008 |
| 7365909 | Fabrication methods for micro compounds optics Methods for fabricating refractive element(s) and aligning the elements in a compound optic, typically to a zone plate element. The techniques are used for fabricating micro refractive, such as Fresnel, optics and compound optics including two or more optical elemen... | 04/29/2008 |
| 7355291 | Overlay marks, methods of overlay mark design and methods of overlay measurements An overlay mark for determining the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The overlay mark includes a plurality of coarsely segmented... | 04/08/2008 |
| 7338885 | Alignment mark and method for manufacturing a semiconductor device having the same In a method for manufacturing a semiconductor device having an alignment mark, a buffer layer is formed on a substrate. A trench is formed at an isolation region of the substrate. The trench is filled with an insulating layer. An alignment groove is formed on the in... | 03/04/2008 |
| 7323393 | Method of reducing film stress on overlay mark An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position o... | 01/29/2008 |
| 7289868 | System and method for calculating a shift value between pattern instances A method comprising adjusting a first relative position between a substrate and a fabrication unit by a first shift value, forming a first pattern relative to a first pattern instance on the substrate subsequent to adjusting the first relative position by the first ... | 10/30/2007 |
| 7282421 | Methods for reducing a thickness variation of a nitride layer formed in a shallow trench isolation CMP process and for forming a device isolation film of a semiconductor device A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at a... | 10/16/2007 |
| 7271073 | Marker for alignment of non-transparent gate layer, method for manufacturing such a marker, and use of such a marker in a lithographic apparatus A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconduc... | 09/18/2007 |
| 7253077 | Substrate, method of preparing a substrate, method of measurement, lithographic apparatus, device manufacturing method and device manufactured thereby, and machine-readable storage medium In a method according to one embodiment of the invention, a plurality of markers are printed in resist on a substrate at a range of angles relative to a crystal axis of the substrate. The markers are etched in to the substrate using an anisotropic etch process, such... | 08/07/2007 |
| 7238592 | Method of manufacturing a semiconductor device having an alignment mark A method of manufacturing a semiconductor device includes providing a substrate and forming a projecting alignment mark. The substrate includes an insulating layer and a semiconductor layer on the insulating layer, and the substrate includes device areas and a scrib... | 07/03/2007 |
| 7235464 | Patterning method The invention relates to a method for creating a pattern on a substrate comprising a first alignment structure, using an elastomeric stamp comprising a patterning structure and a second alignment structure. The method comprises a moving step for moving the elastomer... | 06/26/2007 |
| 7223703 | Method of forming patterns In forming a mask pattern on a circuit board, a mask pattern of N-layer structure is formed in a region where the mechanical strength of the circuit board needs to be increased. N photosensitive layers are first stacked on a substrate so that they becomes lower in s... | 05/29/2007 |
| 7220975 | Mask-making member and its production method, mask and its making method, exposure process, and fabrication method of semiconductor device A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation... | 05/22/2007 |
| 7211460 | Methods for exposing device features on a semiconductor device A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment mar... | 05/01/2007 |
| 7196429 | Method of reducing film stress on overlay mark An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position o... | 03/27/2007 |
| 7192845 | Method of reducing alignment measurement errors between device layers An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on... | 03/20/2007 |
| 7189592 | Manufacturable single-chip hydrogen sensor A robust single-chip hydrogen sensor and a method for fabricating such a sensor. By utilizing an interconnect metallization material that is the same or similar to the material used to sense hydrogen, or that is capable of withstanding an etchant used to pattern a h... | 03/13/2007 |
| 7172948 | Method to avoid a laser marked area step height A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an ina... | 02/06/2007 |
| 7144791 | Lamination through a mask The present invention is a process for transfer of a pattern of material from a donor substrate to a receiver substrate by lamination. The pattern of the transferred material is defined by an aperture in a mask interposed between the donor and receiver during lamina... | 12/05/2006 |
| 7141450 | Flip-chip alignment method Flip-chips are aligned by making a fiducial in the “top” chip that is translucent/transparent to light of a wavelength shorter than infrared, and at least one corresponding fiducial in the “bottom” chip. The top-chip fiducial may be made of a transparent or ... | 11/28/2006 |
| 7115513 | Domain reversal control method for ferroelectric materials A method for forming uniform, sharply defined periodic regions of reversed polarization within a unidirectionally polarized ferroelectric material proceeds as a two-step process. First, alignment keys are formed on upper and lower planar surfaces of a unidirectional... | 10/03/2006 |
| 7105419 | Thin-film semiconductor substrate, method of manufacturing thin-film semiconductor substrate, method of crystallization, apparatus for crystallization, thin-film semiconductor device, and method of manufacturing thin-film semiconductor device A thin-film semiconductor substrate includes an insulative substrate, an amorphous semiconductor thin film that is formed on the insulative substrate, and a plurality of alignment marks that are located on the semiconductor thin film and are indicative of reference ... | 09/12/2006 |
| 7105381 | Wafer alignment method The present invention relates to a wafer alignment method. The wafer alignment method includes the steps of forming first bonding pads and first wafer alignment marks of a convex shape on predetermined regions of a first semiconductor substrate in which a first devi... | 09/12/2006 |
| 7094662 | Overlay mark and method of fabricating the same A method of forming an overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer.... | 08/22/2006 |
| 7091624 | Semiconductor device obtained by dividing semiconductor wafer by use of laser dicing technique and method of manufacturing the same A semiconductor chip is formed by dividing a semiconductor wafer by use of the laser dicing technique. The semiconductor chip has a laser dicing region on the side surface thereof. A dummy wiring layer is formed along the laser dicing region on the surface layer of ... | 08/15/2006 |
| 7091601 | Method of fabricating an apparatus including a sealed cavity A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method is disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabrica... | 08/15/2006 |
| 7083994 | Method of manufacturing a semiconductor device with outline of cleave marking regions and alignment or registration features This invention generally relates to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed o... | 08/01/2006 |
| 7067334 | Tape carrier package and method of fabricating the same A tape carrier package with a widow that is capable of confirming an alignment extent between the tape carrier package and a print wiring board in bonding the tape carrier package mounted with an integrated circuit on the liquid crystal panel and the print wiring bo... | 06/27/2006 |
| 7057300 | Mask, method of producing mask, and method of producing semiconductor device To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a sem... | 06/06/2006 |
| 7052968 | Method and system for aligning IC die to package substrate In a method and system for placing an IC (integrated circuit) die onto a package substrate, a first reference is determined after locating a first fiducial on the package substrate, and a second reference is determined after locating a second fiducial on the package... | 05/30/2006 |
| 7053495 | Semiconductor integrated circuit device and method for fabricating the same A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignm... | 05/30/2006 |
| 7045909 | Alignment mark structure A semiconductor substrate having an upper layer and an alignment mark structure formed on a surface region of the upper layer, the surface region defined by opposite first and second parallel sides extending along the upper layer, outer side walls extending upwardly... | 05/16/2006 |
| 7045434 | Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insula... | 05/16/2006 |
| 7045449 | Methods of forming semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 05/16/2006 |
| 7030772 | Inspection for alignment between IC die and package substrate In a method and system for inspecting alignment between an IC (integrated circuit) die and a package substrate, a plurality of fiducials are located on the package substrate for determining a plurality of references. A center point of the package substrate is determ... | 04/18/2006 |
| 7030508 | Substrate for semiconductor package and wire bonding method using thereof Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a ... | 04/18/2006 |
