Class 438/970 - SPECIFIED ETCH STOP MATERIAL

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Art collection involving the use of a specified material
No. of patents: 190
Last issue date: 04/22/2008

«First «Previous1 2 3 4 5 Next»Last»

Number	Title	Issue Date
7361587	Semiconductor contact and nitride spacer formation system and method The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate conn...	04/22/2008
7195966	Methods of fabricating semiconductor devices including polysilicon resistors and related devices Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating ...	03/27/2007
7187081	Polycarbosilane buried etch stops in interconnect structures Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a p...	03/06/2007
7122467	Method for fabricating semiconductor device Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a firs...	10/17/2006
7022246	Method of fabrication of MIMCAP and resistor at same level A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, ...	04/04/2006
6875687	Capping layer for extreme low dielectric constant films Specific embodiments of the invention provide a silicon-carbide-type or silicon oxycarbide (also often called carbon-doped-oxide [CDO] or organosilicate glass) capping material and method for depositing this capping material on ELK films which are used as a dielectr...	04/05/2005
6815332	Method for forming integrated dielectric layers A method for forming integrated dielectric layers using plasma energy includes (i) depositing a first dielectric layer on a substrate using a first reaction gas comprised of a source gas at a first source gas flow rate and an inert gas at a first inert gas flow rate...	11/09/2004
6724967	Method of making a functional device with deposited layers subject to high temperature anneal A method is disclosed for making a device having one or more deposited layers and subject to a post deposition high temperature anneal. Opposing films having similar mechanical properties are deposited on the front and back faces of a wafer, which is subsequently su...	04/20/2004
6716697	Method of manufacturing semiconductor device having capacitor Provided is a semiconductor device manufacturing method in which the numbers of photolithography and anisotropic dry etching processes are reduced to simplify the manufacturing steps; and it is avoided that the presence of an etching stopper film complicates the man...	04/06/2004
6674111	Semiconductor device having a logic transistor therein An etch stopper member is formed under a cell plate electrode so as to surround an active region along a periphery of the cell plate electrode. The etch stopper member is formed from a material that is resistant to an etchant of a first interlayer insulat...	01/06/2004
6617249	Method for making thin film bulk acoustic resonators (FBARS) with different frequencies on a single substrate and apparatus embodying the method A method for fabricating a resonator, and in particular, a thin film bulk acoustic resonator (FBAR), and a resonator embodying the method are disclosed. An FBAR is fabricated on a substrate by introducing a mass loading top electrode layer. For a substrat...	09/09/2003
6589858	Method of making metal gate stack with etch endpoint tracer layer A metal gate structure and method of making the same provides a tracer layer over a first metal or metal compound layer. When etching a metal gate, formed of tungsten, for example, with a first etchant chemistry optimized for etching tungsten, detection o...	07/08/2003
6555896	Etch stop for use in etching of silicon oxide A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, Si--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing ...	04/29/2003
6548418	Dual layer etch stop barrier A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (Six Ny) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and ...	04/15/2003
6498079	Method for selective source diffusion Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and t...	12/24/2002
6455412	Semiconductor contact via structure and method A contact opening through an insulating layer is filled with metal and etched back to form a metal plug within the opening. A metal interconnect line can then be formed over the contact, and makes electrical contact with the metal plug. Since the contact ...	09/24/2002
6423645	Method for forming a self-aligned contact The present invention discloses a method for forming a self-aligned contact. In the present invention, a amorphous SiC layer or a HexaChloroDisilane-SiN (HCD-SiN) layer is formed on the surface of a transistor as an etching stopper layer. After removing p...	07/23/2002
6417035	Method for manufacturing a field effect transistor It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem ...	07/09/2002
6413846	Contact each methodology and integration scheme A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass mater...	07/02/2002
6410426	Damascene cap layer process for integrated circuit interconnects The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k ...	06/25/2002
6406978	Method of removing silicon carbide A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is forme...	06/18/2002
6391710	Methods of forming capacitors In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and ...	05/21/2002
6331467	Method of manufacturing a trench gate field effect semiconductor device A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the seco...	12/18/2001
6326301	Method for forming a dual inlaid copper interconnect structure A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces (16a, 16b, 20a, and 20b) between these layers (16 and 20) and their ad...	12/04/2001
6309963	Method for manufacturing semiconductor device In a method of manufacturing a semiconductor device wherein the step of forming a titanium film and a titanium nitride film on an aluminum-based alloy film overlying a substrate is carried out for a plurality of such substrates in succession; the titanium...	10/30/2001
6287959	Deep submicron metallization using deep UV photoresist Reflection of incident optical radiation from a highly reflective metal layer (12), such as aluminum, copper or titanium, into a photoresist layer (16) is reduced by interposing a layer of silicon oxynitride (14) between the metal and photoresist layers. ...	09/11/2001
6281130	Method for developing ultra-thin resist films There is provided a method of applying a developing liquid onto a semiconductor wafer substrate having a UTR film thereon so as to minimize unexposed film thickness loss during development. This is achieved by applying the developing liquid from a develop...	08/28/2001
6271133	Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and an...	08/07/2001
6268263	Method of forming a trench type element isolation in semiconductor substrate A trench (21) is formed in a silicon substrate (1) on which an underlying oxide film (2) and a silicon nitride film (3) are formed. Then, a silicon oxide (11) is deposited by an HDP-CVD method to fill the trench (21) with the oxide. Further, a resist (41)...	07/31/2001
6235608	STI process by method of in-situ multilayer dielectric deposition A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silico...	05/22/2001
6232225	Method of fabricating contact window of semiconductor device A method of fabricating a contact window of a semiconductor device, whereby a contact window of a semiconductor device is increased to offset any incline phenomenom and avoid unwanted increase in contact sheet resistance, comprises forming a lower conduct...	05/15/2001
6232139	Method of making suspended thin-film semiconductor piezoelectric devices A process for forming a very thin suspended layer of piezoelectric material of thickness less than 10 microns. The device is made from a combination of GaAs and AlGaAs layers to form either a sensor or an electronic filter. Onto a GaAs substrate is epitax...	05/15/2001
6228760	Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used i...	05/08/2001
6221713	Approach for self-aligned contact and pedestal A method for forming bit-line and charge-node contact holes that eliminates effects of misalignment when contact etching these holes. A liner is deposited that arrests the etch from burning through the deposited polysilicon and damage the word-line and pa...	04/24/2001
6222257	Etch stop for use in etching of silicon oxide A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, Si--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing ...	04/24/2001
6207556	Method of fabricating metal interconnect A method for fabricating a metal interconnect involves forming a first dielectric layer on the substrate having metal lines formed thereon, wherein the top surface of the first dielectric layer is lower than that of the metal line. As a result, the top su...	03/27/2001
6204119	Manufacturing method for a capacitor in an integrated memory circuit A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the firs...	03/20/2001
6204116	Method of fabricating a capacitor with a low-resistance electrode structure in integrated circuit A semiconductor fabrication method is provided for fabricating a capacitor with a low-resistance electrode structure in a mixed-mode integrated circuit (IC) device. The first step is to prepare a semiconductor substrate having a first area where a gate an...	03/20/2001
6190966	Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop laye...	02/20/2001
6172396	ROM structure and method of manufacture A read-only memory structure and method of manufacture comprising the steps of sequentially forming a tunneling oxide layer, a first polysilicon layer, a bottom oxide layer and a silicon nitride layer over a semiconductor substrate having field oxide laye...	01/09/2001

«First «Previous1 2 3 4 5 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Class 438/970 - SPECIFIED ETCH STOP MATERIAL