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| Number | Title | Issue Date |
| 7413963 | Method of edge bevel rinse A method of edge bevel rinse. First, a wafer having a coating material layer disposed thereon is provided. A light beam is optically projected on the wafer to form a reference pattern. The reference pattern defines a central region, and a bevel region surrounding th... | 08/19/2008 |
| 7407824 | Guard ring for improved matching A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the inter... | 08/05/2008 |
| 7407890 | Patterning sub-lithographic features with variable widths A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths ... | 08/05/2008 |
| 7396781 | Method and apparatus for adjusting feature size and position Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sideswalls. The cri... | 07/08/2008 |
| 7368362 | Methods for increasing photo alignment margins Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are ... | 05/06/2008 |
| 7361569 | Methods for increasing photo-alignment margins Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are ... | 04/22/2008 |
| 7341918 | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than tw... | 03/11/2008 |
| 7316978 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 01/08/2008 |
| 7312138 | Semiconductor device and method of manufacture thereof A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 12/25/2007 |
| 7311850 | Method of forming patterned thin film and method of fabricating micro device In a method of forming a patterned thin film, first, an etching stopper film and a film to be patterned are formed in this order on a base layer. Next, a patterned first film is formed on the film to be patterned. Next, a second film is formed over an entire surface... | 12/25/2007 |
| 7297568 | Three-dimensional structural body composed of silicon fine wire, its manufacturing method, and device using same A three-dimensional structure composed of highly-reliable silicon ultrafine wires, a method for producing the three-dimensional structure, and a device including the same are provided. The three-dimensional structure composed of silicon fine wires includes wires ( | 11/20/2007 |
| 7268054 | Methods for increasing photo-alignment margins Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are ... | 09/11/2007 |
| 7259023 | Forming phase change memory arrays A phase change memory may be formed to have a dimension that is sub-lithographic in one embodiment by forming a surface feature over the phase change material, and coating the surface feature with a mask of sub-lithographic dimensions. The horizontal portions of the... | 08/21/2007 |
| 7253057 | Memory cell with reduced size and standby current A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricat... | 08/07/2007 |
| 7253012 | Guard ring for improved matching A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior... | 08/07/2007 |
| 7241683 | Stabilized photoresist structure for etching process A method for forming features in an etch layer is provided. A first mask is formed over the etch layer where the first mask defines a plurality of spaces with widths. The first mask is laterally etched where the etched first mask defines a plurality of spaces with w... | 07/10/2007 |
| 7227171 | Small area contact region, high efficiency phase change memory cell and fabrication method thereof A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction tr... | 06/05/2007 |
| 7186649 | Submicron semiconductor device and a fabricating method thereof A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate;... | 03/06/2007 |
| 7183205 | Method of pitch dimension shrinkage Roughly described, a patterned first layer is provided over a second layer which is formed over a substrate. In a conversion process, first layer material is consumed at feature sidewalls to form third layer material at the feature sidewalls. The width of third laye... | 02/27/2007 |
| 7179748 | Method for forming recesses A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the prot... | 02/20/2007 |
| 7166232 | Method for producing a solid body including a microstructure According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated ... | 01/23/2007 |
| 7157377 | Method of making a semiconductor device using treated photoresist A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is red... | 01/02/2007 |
| 7151040 | Methods for increasing photo alignment margins Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are ... | 12/19/2006 |
| 7122455 | Patterning with rigid organic under-layer For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a... | 10/17/2006 |
| 7115532 | Methods of forming patterned photoresist layers over semiconductor substrates This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has... | 10/03/2006 |
| 7105099 | Method of reducing pattern pitch in integrated circuits A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching... | 09/12/2006 |
| 7071085 | Predefined critical spaces in IC patterning to reduce line end pull back The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a... | 07/04/2006 |
| 7060567 | Method for fabricating trench power MOSFET A method for fabricating trench power MOSFET is described. An epitaxial layer and a mask layer having a first opening are sequentially formed on a substrate. A pair of spacers is formed on the sidewalls of the first opening. A second opening exposing the surface of ... | 06/13/2006 |
| 7026247 | Nanocircuit and self-correcting etching method for fabricating same A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) wi... | 04/11/2006 |
| 7026259 | Liquid-filled balloons for immersion lithography A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in ... | 04/11/2006 |
| 7015139 | Two-dimensionally arrayed quantum device A quantum device is constituted from a two-dimensional array of quantum dots formed from metal atom aggregates contained in a metalloprotein complex. The metalloprotein is arranged on the surface of a substrate having an insulation layer with a pitch of the size of ... | 03/21/2006 |
| 6962825 | Exposure apparatus Disclosed is an exposure apparatus for printing, by exposure, a pattern of an original on a substrate, which includes a housing tightly filled with a predetermined ambience and for accommodating therein at least a portion of an exposure light optical axis, and a det... | 11/08/2005 |
| 6955961 | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution A method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution controls the defined pitches of the target layer by use of polymer spacer, photo-insensitive polymer plug and polymer mask during the process, so as to achieve the min... | 10/18/2005 |
| 6946391 | Method for forming dual damascenes A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to... | 09/20/2005 |
| 6924191 | Method for fabricating a gate structure of a field effect transistor A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more... | 08/02/2005 |
| 6887395 | Method of forming sub-micron-size structures over a substrate A method is provided for forming sub-micron-size structures over a substrate. A width-defining step is formed over the substrate. A width-defining layer is formed over an edge of the width-defining step. The width-defining layer is etched back to leave a spacer adja... | 05/03/2005 |
| 6878646 | Method to control critical dimension of a hard masked pattern A method of reducing the critical dimension (CD) of a hard mask by a wet etch method is described. An oxide hard mask is treated with a H2SO4/H2O2 (SPM) solution followed by treatment with a NH4OH/H2O... | 04/12/2005 |
| 6869899 | Lateral-only photoresist trimming for sub-80 nm gate stack The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or n... | 03/22/2005 |
| 6858542 | Semiconductor fabrication method for making small features A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed featur... | 02/22/2005 |
| 6849487 | Method for forming an electronic structure using etch A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first l... | 02/01/2005 |
