Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 7436029 | High performance CMOS device structures and method of manufacture A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width... | 10/14/2008 |
| 7396747 | Hetero-integrated strained silicon n- and p-MOSFETs The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs a... | 07/08/2008 |
| 7393735 | Structure for and method of fabricating a high-mobility field-effect transistor A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects... | 07/01/2008 |
| 7361559 | Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The sour... | 04/22/2008 |
| 7335545 | Control of strain in device layers by prevention of relaxation The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance. ... | 02/26/2008 |
| 7326599 | Gate material for semiconductor device fabrication In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by... | 02/05/2008 |
| 7314793 | Technique for controlling mechanical stress in a channel region by spacer removal During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions m... | 01/01/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7306997 | Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spa... | 12/11/2007 |
| 7288451 | Method and structure for forming self-aligned, dual stress liner for CMOS devices A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of th... | 10/30/2007 |
| 7282414 | Fabrication methods for compressive strained-silicon and transistors using the same Fabrication methods for compressive strained-silicon by ion implantation. Ions are implanted into a silicon-containing substrate and high temperature processing converts the vicinity of the ion-contained region into strained-silicon. Transistors fabricated by the me... | 10/16/2007 |
| 7273800 | Hetero-integrated strained silicon n- and p-MOSFETs The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs a... | 09/25/2007 |
| 7262087 | Dual stressed SOI substrates The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered sta... | 08/28/2007 |
| 7226834 | PMD liner nitride films and fabrication methods for improved NMOS performance Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride l... | 06/05/2007 |
| 7223647 | Method for forming integrated advanced semiconductor device using sacrificial stress layer An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS tra... | 05/29/2007 |
| 7220626 | Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; fo... | 05/22/2007 |
| 7195969 | Strained channel CMOS device with fully silicided gate electrode A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including pol... | 03/27/2007 |
| 7186302 | Fabrication of nonpolar indium gallium nitride thin films, heterostructures and devices by metalorganic chemical vapor deposition A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet ... | 03/06/2007 |
| 7157355 | Method of making a semiconductor device having a strained semiconductor layer An implant is performed in the P channel regions, while masking the N channel regions, to deeply amorphize a layer at the surface of a semiconductor layer. After this amphorization step, germanium is implanted into the amorphized layer. The germanium is implanted to... | 01/02/2007 |
| 7153763 | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at le... | 12/26/2006 |
| 7138310 | Semiconductor devices having strained dual channel layers A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained... | 11/21/2006 |
| 7109096 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device including: providing a substrate having an insulating layer and a single crystal silicon layer formed on the insulating layer; forming a strain-inducing semiconductor layer on the single crystal silicon layer, the str... | 09/19/2006 |
| 7101765 | Enhancing strained device performance by use of multi narrow section layout A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respecti... | 09/05/2006 |
| 7074655 | Gate material for semiconductor device fabrication In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by... | 07/11/2006 |
| 7074686 | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diff... | 07/11/2006 |
| 7060582 | Adjusting the germanium concentration of a semiconductor layer for equal thermal expansion for a hetero-junction bipolar transistor device The present invention relates to a semiconductor layer applicable to a hetero-junction bipolar transistor, a forming method thereof, and a semiconductor device and a manufacturing method thereof, for example. The semiconductor layer and the forming method thereof ac... | 06/13/2006 |
| 7037794 | Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack... | 05/02/2006 |
| 6991972 | Gate material for semiconductor device fabrication In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by... | 01/31/2006 |
| 6987065 | Method of manufacturing self aligned electrode with field insulation The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at on... | 01/17/2006 |
| 6972245 | Method for co-fabricating strained and relaxed crystalline and poly-crystalline structures One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substra... | 12/06/2005 |
| 6916694 | Strained silicon-channel MOSFET using a damascene gate process The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introd... | 07/12/2005 |
| 6893986 | Method of reducing internal stress in materials Methods are provided for adjusting and controlling the stress between layers of material in a multilayer structure. A first stress is configured in a region of stress on the substrate material. A second material is then deposited over the substrate. A second stress ... | 05/17/2005 |
| 6890816 | Compound semiconductor structure including an epitaxial perovskite layer and method for fabricating semiconductor structures and devices High quality epitaxial layers of monocrystalline perovskite materials (18) can be grown overlying monocrystalline substrates (12) such as gallium arsenide wafers by forming a metal template layer (16) on the monocrystalline substrate. The struct... | 05/10/2005 |
| 6812074 | SOI field effect transistor element having a recombination region and method of forming same An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment,... | 11/02/2004 |
| 6756325 | Method for producing a long wavelength indium gallium arsenide nitride(InGaAsN) active region Several methods for producing an active region for a long wavelength light emitting device are disclosed. In one embodiment, the method comprises placing a substrate in an organometallic vapor phase epitaxy (OMVPE) reactor, the substrate for supporting growth of an ... | 06/29/2004 |
| 6709909 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes formi... | 03/23/2004 |
| 6709903 | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing A method to obtain thin ( | 03/23/2004 |
| 6706585 | Chemical vapor deposition process for fabricating layered superlattice materials A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompo... | 03/16/2004 |
| 6696313 | Method for aligning quantum dots and semiconductor device fabricated by using the same A method for aligning quantum dots effectively controls a growth position of the quantum dots for obviating an irregularity of a position of spontaneous formation quantum dots, and thus aligns the quantum dots in one-dimension (1-D) or two-dimension (2-D)... | 02/24/2004 |
| 6649478 | Semiconductor device and method of manufacturing same A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconduc... | 11/18/2003 |
