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| Number | Title | Issue Date |
| 7018856 | Calibration standards for dopants/impurities in silicon and preparation method A multi-point calibration standards and a method of fabricating calibration standards which are used to quantify the dose or concentration of a dopant or impurity in a silicon matrix. The calibration standards include a set of calibration standard wafers for each do... | 03/28/2006 |
| 6579730 | Monitoring process for oxide removal Generally, a method for monitoring a process of removing native oxides from an at least partially exposed layer disposed on a substrate is provided. In one embodiment, a method for monitoring includes disposing the substrate in a process chamber, exposing... | 06/17/2003 |
| 6218301 | Deposition of tungsten films from W(CO)6 A method of forming tungsten films on oxide layers is disclosed. The tungsten films are formed on the oxide layers by treating the oxide using a silane based gas mixture followed by the thermal decomposition of a W(CO)6 precursor. After the W(C... | 04/17/2001 |
| 6043143 | Ohmic contact and method of manufacture A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n... | 03/28/2000 |
| 5872017 | In-situ epitaxial passivation for resistivity measurement A method for preparing an epitaxial silicon wafer in a reactor is provided. The method comprises the steps of depositing an epitaxial layer on a surface of a silicon wafer contained in the reactor at an elevated temperature; purging the reactor with hydro... | 02/16/1999 |
| 5728598 | Method of manufacturing a SRAM cell having a low stand-by current The present invention relates to a method of fabricating a SRAM cell that has a low stand-by current. A second polysilicon layer which is used as polysilicon resistor is exactly over a first polysilicon layer. The double polysilicon layer is utilized to r... | 03/17/1998 |
| 5721150 | Use of silicon for integrated circuit device interconnection by direct writing of patterns therein An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon... | 02/24/1998 |
| 5686359 | Titanium silicide process The specification describes a process for siliciding silicon metallization with titanium. The process requires two anneal steps and is based on careful control of operating parameters during the first anneal step. A prescription is given relating time and... | 11/11/1997 |
| 5679607 | Method of manufacturing a damage free buried contact using salicide technology A manufacturing process for a CMOS cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer ... | 10/21/1997 |
| 5652151 | Method for determining an impurity concentration profile Impurity concentration profile is determined for a diffused layer of a semiconductor substrate by repeating a combination of etching of the diffused layer and measuring sheet resistance and/or hall resistance by using electrodes formed on the diffused lay... | 07/29/1997 |
| 5624869 | Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material struct... | 04/29/1997 |
| 5624871 | Method for making electrical local interconnects A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing condu... | 04/29/1997 |
| 5620920 | Process for fabricating a CMOS structure with ESD protection A process is disclosed for fabricating a CMOS structure with ESD protection. The outside transistors are covered with a protective oxide layer which is so masked as to cover the areas of the respective source and drain regions adjoining the field-oxide re... | 04/15/1997 |
| 5578504 | Method for determination of resistivity of N-type silicon epitaxial layer A method for the determination of the resistivity of an n-type epitaxial layer formed on a silicon substrate is disclosed. This invention resides in either directly determining the true resistivity of a sample by preparing this sample without a natural ox... | 11/26/1996 |
| 5563100 | Fabrication method of semiconductor device with refractory metal silicide formation by removing native oxide in hydrogen A fabrication method of a semiconductor device in which a refractory metal silicide film with a low sheet-resistance can be produced. First, a substructure made of Si-contained material is prepared, the surface of which is covered with a native SiO2 | 10/08/1996 |
| 5506167 | Method of making a high resistance drain junction resistor in a SRAM An improved SRAM resistor structure having implanted therein ions of an material in the surface layer of a drain junction region juxtaposed to an overlying metal contact layer providing the benefits of high resistance, low energy consumption, a single ion... | 04/09/1996 |
| 5494845 | Method of fabrication of bilayer thin film resistor A bilayer thin film resistor and a method of fabricating such as resistor. A layer of a resistive material such as titanium tungsten is sputter deposited on a substrate before depositing a relatively thick overlayer of a material such as chromium silicon ... | 02/27/1996 |
| 5489547 | Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50)... | 02/06/1996 |
| 5468974 | Control and modification of dopant distribution and activation in polysilicon Dopant distribution and activation in polysilicon is controlled by implanting electrically neutral atomic species which accumulate along polysilicon grain boundaries. Exemplary atomic species include noble gases and Group IV elements other than silicon.... | 11/21/1995 |
| 5320977 | Method and apparatus for selecting the resistivity of epitaxial layers in III-V devices A novel heterostructure acoustic charge transport (HACT) device is disclosed having an optimized charge density. The device includes a transducer fabricated on a substrate structure that launches surface acoustic waves. A reflector is formed in the substr... | 06/14/1994 |
| 5308789 | Method of preparing diffused silicon device substrate In a method of preparing a diffused silicon device substrate for use in the fabrication of a MOS power device, a drive-in diffusion step is followed by a thermal donor formation heat treatment which is achieved by heating the silicon device substrate at a... | 05/03/1994 |
| 5302552 | Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed A method of manufacturing a semiconductor device whereby a layer (12) containing Co or Ni is deposited on a surface (2) of a semiconductor body (1) bounded by silicon regions (3, 4, 5, 6) and regions of insulating material (8, 9), after which the semicond... | 04/12/1994 |
| 5268330 | Process for improving sheet resistance of an integrated circuit device gate A passivating layer is deposited over an integrated circuit device, conventionally fabricated using silicidation, after which an insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivating layer above t... | 12/07/1993 |
| 5232865 | Method of fabricating vertically integrated oxygen-implanted polysilicon resistor A method for fabricating a high value, vertically integrated resistor begins with an integrated circuit having an unpassivated upper surface that includes designated circuit nodes to be placed in series with the vertical resistor. A layer of passivating m... | 08/03/1993 |
| 5217907 | Array spreading resistance probe (ASRP) method for profile extraction from semiconductor chips of cellular construction A method of extracting an impurity profile from a diced semiconductor chip having cellular construction. The cells are arranged in a matrix the columns and rows of which have a defined column pitch ax and a defined row spacing ay. In... | 06/08/1993 |
| 5173443 | Method of manufacture of optically transparent electrically conductive semiconductor windows Methods are disclosed for making semiconductor windows which are transparent to light in the infrared range which have good electrical conductivity and are formed of a substrate material (11) having a semiconductor coating (14) having a dopant included th... | 12/22/1992 |
| 5169806 | Method of making amorphous deposited polycrystalline silicon thermal ink jet transducers A resistive heating element is formed by depositing an amorphous silicon film on selected portions of a substrate and heating the deposited amorphous silicon film so that it undergoes solid phase epitaxy to form a (111) textured polycrystalline silicon fi... | 12/08/1992 |
| 5158909 | Method of fabricating a high voltage, high speed Schottky semiconductor device A high voltage, high speed Schottky diode has an electrode of aluminum or like Schottky barrier metal formed on a semiconductor region to create a Schottky barrier therebetween. Also formed on the semiconductor region is a extremely thin resisitve layer o... | 10/27/1992 |
| 5112774 | Method of fabricating a high-voltage semiconductor device having a rectifying barrier A semiconductor device such as a Schottky-barrier rectifier diode is disclosed which has a barrier electrode formed on a semiconductor substrate of gallium arsenide or the like. Formed around the barrier electrode is an annular resistive layer, typically ... | 05/12/1992 |
| 5110758 | Method of heat augmented resistor trimming An improved method of trimming resistors by metal migration by local heating (18,21) of the resistor (23) to allow a reduced level of electric current to be used. The resistor is then trimmed by application of short pulses of high current causing metal mi... | 05/05/1992 |
| 5082792 | Forming a physical structure on an integrated circuit device and determining its size by measurement of resistance A structure is formed on an electronic integrated circuit by altering the electrical characteristics of a diffused region of a substrate through a contact hole (window) in an insulating layer, in proportion to the size of said contact hole, such that the ... | 01/21/1992 |
| 5051376 | Method for producing semiconductor device and semiconductor device produced thereby A method for producing a semiconductor device comprises the steps of: preparing a IIIb -Vb group compound single crystalline semiconductor substrate produced by a liquid encapsulated Czochralski process, the single crystalline semico... | 09/24/1991 |
| 5023201 | Selective deposition of tungsten on TiSi2 An improved process for preparing selective deposition of conductive metals on disilicide encroachment barriers allows the construction of integrated circuit components wherein the metal/disilicide interface is substantially free of O and/or F contaminati... | 06/11/1991 |
| 5013690 | Method for deposition of silicon films from azidosilane sources A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550° C. to about 750° C. in a chemical vapor deposition reactor havi... | 05/07/1991 |
| 4999315 | Method of controlling dopant incorporation in high resistivity In-based compound Group III-V epitaxial layers High resistivity In-based compound Group III-V epitaxial layers are used to prevent substantial current flow through a region of a semiconductor device, such as a CSBH, DCPBH, EMBH or CMBH laser, a LED, a photodiode, a HBT, or a FET. Also disclosed is a h... | 03/12/1991 |
| 4965214 | Method for manufacturing poly-crystal sillicon having high resistance Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer h... | 10/23/1990 |
| 4916507 | Polysilicon resistor implanted with rare gas A method of fabricating a resistor in a polycrystalline semiconductor material includes rendering the material conductive by a heavy doping implantation of ions which are electrically active with respect to the material. Ions which are electrically inacti... | 04/10/1990 |
| 4891201 | Ultra-pure epitaxial silicon Production of epitaxial silicon by thermal decomposition or hydrogen reduction of bromosilanes or iodosilane is disclosed.... | 01/02/1990 |
| 4835118 | Non-destructive energy beam activated conductive links A process of manufacturing selectively restructurable conductive links between circuit elements and corresponding spare elements on a semiconductor. A continuous green light laser directed at a non-conductive amorphous region in the links causes the regio... | 05/30/1989 |
| 4762801 | Method of fabricating polycrystalline silicon resistors having desired temperature coefficients A method of fabricating polycrystalline silicon resistors having nearly zero or positive temperature coefficient includes the steps of depositing a layer of polycrystalline silicon, implanting the layer with silicon to make the layer substantially amorpho... | 08/09/1988 |
