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Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 7422977 | Copper adhesion improvement device and method A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper... | 09/09/2008 |
| 7327031 | Semiconductor device and method of manufacturing the same There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in t... | 02/05/2008 |
| 7235882 | Semiconductor device having a wiring layer of damascene structure and method for manufacturing the same In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier... | 06/26/2007 |
| 7229923 | Multi-step process for forming a barrier film for use in copper layer formation Methods for forming robust copper structures include steps for providing a substrate with an insulating layer with openings formed therein. At least two barrier layers are then formed followed by the deposition of a copper seed layer which is annealed. Bulk copper d... | 06/12/2007 |
| 7224006 | Semiconductor device A semiconductor device includes: a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities; an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and a shared line which con... | 05/29/2007 |
| 7214613 | Cross diffusion barrier layer in polysilicon A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of sec... | 05/08/2007 |
| 7157795 | Composite tantalum nitride/tantalum copper capping layer Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments incl... | 01/02/2007 |
| 7098054 | Method and structure for determining thermal cycle reliability A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is ... | 08/29/2006 |
| 7083871 | Single-sided sputtered magnetic recording disks An information-storage media is provided that includes: (a) a substrate disk 312 having first and second opposing surfaces; (b) a first selected layer 304 on the first surface, the first selected sele... | 08/01/2006 |
| 7052993 | Thin film transistor having copper alloy wire and method of manufacturing the same A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the copper all... | 05/30/2006 |
| 6777328 | Method of forming multilayered conductive layers for semiconductor device A method of manufacturing a semiconductor device including forming an insulator layer on an integrated circuit, forming a barrier layer having a first titanium film and a titanium nitride film on the insulator layer, heat-treating the barrier layer to release nitrog... | 08/17/2004 |
| 6750108 | Method for manufacturing a semiconductor device A method for manufacturing a semiconductor device comprises: (a) forming a dummy gate provided with a sidewall spacer at its side wall and an anti-silicidation film thereon on a semiconductor substrate, as well as forming a source/drain region on the surface ... | 06/15/2004 |
| 6686661 | Thin film transistor having a copper alloy wire A thin film transistor and a method of manufacturing the same includes forming a copper alloy line on substrate, an oxidation film formed on the upper surface of the copper alloy line. The copper alloy line includes a concentration y of magnesium, and the... | 02/03/2004 |
| 6531780 | Via formation in integrated circuit interconnects An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A first channel dielectric layer over the semiconductor has a first opening lined by a first barrier layer and filled by a fi... | 03/11/2003 |
| 6498397 | Seed layer with annealed region for integrated circuit interconnects An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An barrier layer lines the opening ... | 12/24/2002 |
| 6498086 | Use of membrane properties to reduce residual stress in an interlayer region A method and apparatus comprising thinning a substrate sufficiently to allow it to be mechanically compliant with a material deposited on its surface is disclosed. The mechanical compliance allows a reduction in the interlayer stress generated by dissimil... | 12/24/2002 |
| 6424046 | Substrate for manufacturing a semiconductor device with three element alloy The substrate according to the present invention is comprised of a silver/gold/grain element alloy layer, wherein the alloy forms an outside layer of the product. The grain element is selected from a group consisting of selenium, antimony, bismuth, nickel... | 07/23/2002 |
| 6410412 | Methods for fabricating memory devices Methods for fabricating memory devices having a multi-dot floating gate ensuring a desirable crystallization of a semiconductor film without ruining the flatness of the surface of the polycrystallized silicon layer and a tunnel oxide film, allowing desira... | 06/25/2002 |
| 6391754 | Method of making an integrated circuit interconnect A method of encapsulating metal lines (130, 132, 134, 136, 138) by implantation of dopants to form surface regions (131, 133, 135, 137, 139) after the metal lines have been fabricated. The surface regions may act as passivation layers and electromigration... | 05/21/2002 |
| 6306732 | Method and apparatus for simultaneously improving the electromigration reliability and resistance of damascene vias using a controlled diffusivity barrier An apparatus for improving electromigration reliability and resistance of a single- or dual-damascene via includes an imperfect barrier formed at the bottom of the via, and a stronger barrier formed at all other portions of the via. The imperfect barrier ... | 10/23/2001 |
| 6268273 | Fabrication method of single electron tunneling device A method of fabricating a single electron tunneling (SET) device, the method including forming a source electrode and a drain electrode a predetermined distance apart from each other on an insulating substrate, forming a metal layer having a thickness on ... | 07/31/2001 |
| 6261963 | Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first openin... | 07/17/2001 |
| 6204167 | Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer A multi-level wiring structure having: a first wiring formed on an insulating surface, the first wiring containing refractory metal as a main composition thereof; an inter-level insulating film formed to cover the first wiring and having a contact hole at... | 03/20/2001 |
| 6200894 | Method for enhancing aluminum interconnect properties A method of enhancing the aluminum interconnect properties in very fine metalization patterns interconnecting integrated circuits that improves the texture and electromigration resistance of aluminum in thin films. Enhanced performance can be obtained by ... | 03/13/2001 |
| 6150041 | Thick-film circuits and metallization process 16 A thick-film circuit (10) includes an electrically conductive substrate (12), such as stainless steel, and a first layer of a gold-rich conductor (15) applied directly thereon. The gold layer is fired in a non-oxidizing atmosphere, such as nitrogen, to... | 11/21/2000 |
| 6144097 | Semiconductor device and method of fabricating the same A semiconductor device comprising a semiconductor substrate including an electronic element, interlayer dielectric (silicon oxide layer and BPSG layer) formed on the semiconductor substrate, a contact hole formed in the interlayer dielectric, a barrier la... | 11/07/2000 |
| 6114236 | Process for production of semiconductor device having an insulating film of low dielectric constant A process for producing a semiconductor device having an interlayer insulating film of low dielectric constant and interconnects of low resistance and operable at a high speed, which comprises: a step of heat-treating a semiconductor substrate having a lower ... | 09/05/2000 |
| 6110819 | Interconnect structure using Al2 Cu for an integrated circuit chip An interconnect structure and method for an integrated circuit chip for resisting electromigration is described incorporating patterned interconnect layers of Al or Al--Cu and interlayer contact regions or studs of Al2 Cu between patterned inte... | 08/29/2000 |
| 6072945 | System for automated electromigration verification An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are pro... | 06/06/2000 |
| 6057238 | Method of using hydrogen and oxygen gas in sputter deposition of aluminum-containing films and aluminum-containing films derived therefrom An aluminum-containing film having an oxygen content within the film. The aluminum-containing film is formed by introducing hydrogen gas and oxygen gas along with argon gas into a sputter deposition vacuum chamber during the sputter deposition of aluminum... | 05/02/2000 |
| 5993908 | Method of producing an aluminum film A method of producing an aluminum film on a substrate, from which very narrow aluminum conductor tracks can be created that are highly resistant to electromigration and/or stress migration. The substrate with the polycrystalline aluminum film is cooled in... | 11/30/1999 |
| 5981378 | Reliable interconnect via structures and methods for making the same Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A seco... | 11/09/1999 |
| 5963831 | Method of making an interconnect structure employing equivalent resistance paths to improve electromigration resistance A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column co... | 10/05/1999 |
| 5963729 | Method for automated electromigration verification An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propag... | 10/05/1999 |
| 5959360 | Interconnect structure employing equivalent resistance paths to improve electromigration resistance A structure of a conductive line. The structure of a conductive line comprises a substrate with two conductive lines formed thereon. These two conductive lines are isolated by the formation of a dielectric layer. The conductive lines are electrically conn... | 09/28/1999 |
| 5930587 | Stress migration evaluation method A method for accurately and objectively evaluating stress migration effects on long term reliability of integrated circuits. A sample containing a conductive runner is fabricated according to a given fabrication process. The fabricated sample undergoes a ... | 07/27/1999 |
| 5913145 | Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures In order to provide a thermally stable diffusion barrier for a contact, a layer of titanium is formed on the patterned substrate. A layer of tungsten nitride is formed on the titanium layer. After an annealing step, an interfacial layer and a layer of tit... | 06/15/1999 |
| 5891802 | Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects There is provided an improved metallization stack structure and a method for fabricating the same so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper... | 04/06/1999 |
| 5759868 | Aluminum interconnection An aluminum interconnection of the invention contains scandium as an impurity, so that the hardness of the interconnection is improved. Moreover, after a thin Al--Sc alloy film is formed, an annealing is performed so as to make the crystal grain larger th... | 06/02/1998 |
| 5736460 | Method of fabricating semiconductor device including gold interconnections where the gold grain size is a function of the width of the interconnections In a semiconductor device having gold interconnections for connecting elements formed on a substrate with each other, the improvement is that the average dimension of gold grains constituting the gold interconnections is determined to be 0.17 through 0.25... | 04/07/1998 |
