Class 438/926 - DUMMY METALLIZATION

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Art collection involving the use of an electrically conductive
No. of patents: 143
Last issue date: 07/15/2008

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Number	Title	Issue Date
7399675	Electronic device including an array and process for forming the same An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can ...	07/15/2008
7361574	Single-crystal silicon-on-glass from film transfer A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the s...	04/22/2008
7332439	Metal gate transistors with epitaxial source and drain regions An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor. ...	02/19/2008
7314811	Method to make corner cross-grid structures in copper metallization A new method to prevent cracking at the corners of a semiconductor die during dicing is described. Dummy metal structures are fabricated at the corners of the die to prevent cracking. The design for the dummy metal structures can be generated automatically by a comp...	01/01/2008
7298015	Three-dimensional structure element and method of manufacturing the element, optical switch, and micro device A three-dimensional structure element having a plurality of three-dimensional structural bodies and capable of being uniformly formed without producing a dispersion in shape of the three-dimensional structural bodies, comprising a substrate (11) and the three...	11/20/2007
7271045	Etch stop and hard mask film property matching to enable improved replacement metal gate process A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material...	09/18/2007
7247530	Ultrathin SOI transistor and method of making the same A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning a...	07/24/2007
7226839	Method and system for improving the topography of a memory array A method and system for improving the topography of a memory array is disclosed. In one embodiment, a dummy bitline is formed over a field oxide region at an interface between a memory array and interface circuitry. In addition, a poly-2 layer is applied above the d...	06/05/2007
7217644	Method of manufacturing MOS devices with reduced fringing capacitance An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate diel...	05/15/2007
7217611	Methods for integrating replacement metal gate structures Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate mate...	05/15/2007
7214994	Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ...	05/08/2007
7211492	Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ...	05/01/2007
7193269	MOS semiconductor device While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor...	03/20/2007
7186639	Metal interconnection lines of semiconductor devices and methods of forming the same Metal interconnection lines of semiconductor devices and methods of forming the same are disclosed. Improved reliability is achieved in a disclosed metal line of a semiconductor device by preventing metal layers from eroding and preventing metal lines from being des...	03/06/2007
7176090	Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider...	02/13/2007
7163853	Method of manufacturing a capacitor and a metal gate on a semiconductor device A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom elec...	01/16/2007
7160794	Method of fabricating non-volatile memory A method for manufacturing a non-volatile memory. The method comprises steps of forming a first dielectric layer on a substrate and forming a dummy gate layer on the first dielectric layer. Further, the dummy gate layer is defined to form a plurality of dummy gates ...	01/09/2007
7157289	Method for homogenizing the thickness of a coating on a patterned layer A method for homogenizing the thickness of a uniform layer deposited on a layer of a material etched according to functional patterns, consisting of filling the empty areas with dummy patterns; a function, providing the thickness variation of the uniform layer for a...	01/02/2007
7074710	Method of wafer patterning for reducing edge exclusion zone A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the ra...	07/11/2006
7071063	Dual-bit non-volatile memory cell and method of making the same A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one fir...	07/04/2006
7002256	Semiconductor device having wiring patterns and dummy patterns covered with insulating layer A semiconductor device including a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area, circuit patterns formed on the substrate in the circuit area, a first dummy pattern...	02/21/2006
6998682	Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension A MOSFET device structure formed on a silicon on insulator layer, and a process sequence employed to fabricate said MOSFET device structure, has been developed. The process features insulator filled, shallow trench isolation (STI) regions formed in specific location...	02/14/2006
6972225	integrating n-type and P-type metal gate transistors At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal...	12/06/2005
6955987	Comparison of chemical-mechanical polishing processes Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16	10/18/2005
6953719	Integrating n-type and p-type metal gate transistors At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal...	10/11/2005
6951806	Metal region for reduction of capacitive coupling between signal lines A structure includes a substrate, first and second signal lines above the substrate, where unused substrate surface area exists between the first and second signal lines, and a first shield line in the unused substrate surface area. To define the first shield line, ...	10/04/2005
6943129	Interconnection structure and method for designing the same A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-fi...	09/13/2005
6939726	Via array monitor and method of monitoring induced electrical charging An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated du...	09/06/2005
6930382	Semiconductor device and method of manufacturing the same A semiconductor device includes a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and elect...	08/16/2005
6916705	Semiconductor memory and method for fabricating the same In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper b...	07/12/2005
6884670	Dry etching with reduced damage to MOS device A method of manufacturing a semiconductor device having an insulated gate type field effect transistor. A gate insulating film, a gate electrode layer having a predetermined area and facing the semiconductor substrate with the gate insulating film being interposed t...	04/26/2005
6867080	Polysilicon tilting to prevent geometry effects during laser thermal annealing A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to “fill in...	03/15/2005
6858483	Integrating n-type and p-type metal gate transistors At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal...	02/22/2005
6849549	Method for forming dummy structures for improved CMP and reduced capacitance A method for forming a damascene structure to improve a chemical mechanical polishing (CMP) process while reducing the capacitance in an integrated circuit including forming a shallow dummy damascene adjacent active damascenes and removing the dummy damascene in a C...	02/01/2005
6833622	Semiconductor topography having an inactive region formed from a dummy structure pattern A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dum...	12/21/2004
6791191	Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such “trick” via would force a reverse engin...	09/14/2004
6780715	Method for fabricating merged dram with logic semiconductor device A method is disclosed for fabricating an MDL (Merged DRAM Logic) semiconductor device, in which silicide is formed on a logic region and a memory region selectively for enhancing device reliability. The method includes the steps of (a) providing a substrate having a...	08/24/2004
6782512	Fabrication method for a semiconductor device with dummy patterns A semiconductor device is fabricated by a method that includes forming a conductive pattern on a semiconductor substrate, covering the conductive pattern with a dielectric layer, and planarizing the dielectric layer by chemical-mechanical polishing. To avoid global ...	08/24/2004
6743644	Method of making a metallization line layout The present invention relates to metallization line layouts that minimize focus offset sensitivity by a substantial elimination of thin isolated metallization line segments that are inadequately patterned during formation of a mask. The present invention also relate...	06/01/2004
6737351	Versatile system for diffusion limiting void formation Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure (406, 506) within a semiconductor device (400, 500). The device typically comprises a first interconnect (402, 502), and a second interconnect (4...	05/18/2004

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Class 438/926 - DUMMY METALLIZATION