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| Number | Title | Issue Date |
| 8129292 | Integrated circuit arrangement with shockley diode or thyristor and method for production and use of a thyristor An integrated circuit arrangement includes a Shockley diode or a thyristor. An inner region of the diode or of the thyristor is completely or partially shielded during the implantation of a p-type well. This gives rise to a Shockley diode or a thyristor having impro... | 03/06/2012 |
| 7435669 | Method of fabricating transistor in semiconductor device A method of fabricating a transistor in a semiconductor device. A gate oxide layer and a gate are formed on a semiconductor substrate. An oxide layer and a silicon nitride layer are stacked on the substrate. The stacked oxide and silicon nitride layers are etched ba... | 10/14/2008 |
| 7265039 | Method for fabricating semiconductor device with improved refresh time The present invention relates to a method for fabricating a semiconductor device with improved refresh time. The method includes the steps of: forming a plurality of gate lines on a substrate; forming a plurality of cell junctions by ion-implanting a first dopant wi... | 09/04/2007 |
| 7157357 | Methods of forming halo regions in NMOS transistors Disclosed are methods of forming a halo region in n-channel type MOS (NMOS) transistors. In one example, the method includes forming, on a channel region of a semiconductor substrate, a structure having a gate insulation film pattern and a gate conductive film patte... | 01/02/2007 |
| 6958257 | Tantalum sputtering target and method of manufacture Described is a method for producing high purity tantalum, the high purity tantalum so produced and sputtering targets of high purity tantalum. The method involves purifying starting materials followed by subsequent refining into high purity tantalum. ... | 10/25/2005 |
| 6955958 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device is disclosed. An oxide layer for regulating ion-implantation is formed before the implantation of the impurities into a predetermined region of a P-lightly doped drained (LDD) to regulate the implantation state of P t... | 10/18/2005 |
| 6951806 | Metal region for reduction of capacitive coupling between signal lines A structure includes a substrate, first and second signal lines above the substrate, where unused substrate surface area exists between the first and second signal lines, and a first shield line in the unused substrate surface area. To define the first shield line, ... | 10/04/2005 |
| 6921709 | Front side seal to prevent germanium outgassing A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrat... | 07/26/2005 |
| 6849529 | Deep-trench capacitor with hemispherical grain silicon surface and method for making the same A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrif... | 02/01/2005 |
| 6809016 | Diffusion stop implants to suppress as punch-through in SiGe Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant ju... | 10/26/2004 |
| 6797596 | Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device A method used during the formation of a semiconductor device reduces ion channeling during implantation of the wafer. The method comprises providing a semiconductor wafer and an unetched transistor gate stack assembly over the wafer. The unetched transistor gate sta... | 09/28/2004 |
| 6794277 | Method of doping semiconductor layer, method of manufacturing thin film semiconductor device, and thin film semiconductor device A lower concentration impurity diffusion region can be formed under excellent control, even when a low heat-resistant substrate is used. At the time of doping a semiconductor layer, a mask such as sidewalls (24) where an energy beam passes through, is formed ... | 09/21/2004 |
| 6762099 | Method for fabricating buried strap out-diffusions of vertical transistor A two-stage method for making buried strap out-diffusions is disclosed. A substrate having a deep trench is provided. A first conductive layer is deposited at the bottom of the deep trench. A collar oxide is formed on sidewalls of the deep trench. A second conductiv... | 07/13/2004 |
| 6695903 | Dopant pastes for the production of p, p+, and n, n+ regions in semiconductors The invention relates to novel boron, phosphorus or boron-aluminium dopant pastes for the production of p, p+ and n, n+ regions in monocrystalline and polycrystalline Si wafers, and of corresponding pastes for use as masking pastes in semiconductor fabric... | 02/24/2004 |
| 6645839 | Method for improving a doping profile for gas phase doping A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping... | 11/11/2003 |
| 6518113 | Doping of thin amorphous silicon work function control layers of MOS gate electrodes Work function control layers are provided in in-laid, metal gate electrode, Si-based MOS transistors and CMOS devices by a process which avoids deleterious dopant implantation processing resulting in damage to the thin gate insulator layer and undesirable... | 02/11/2003 |
| 6498079 | Method for selective source diffusion Deep profile and highly doped impurity regions can be formed by diffusing from a solid source or doped silicon glass and using a patterned nitride layer. An oxide etch stop and polysilicon sacrificial layer are left in place in the patterned regions and t... | 12/24/2002 |
| 6489209 | Manufacturing method of LDD-type MOSFET After a first insulating film is formed only on the top surface or at least on the entire surface of a polysilicon gate electrode, first impurity ions are implanted into a semiconductor substrate from above the entire substrate to provide lightly doped so... | 12/03/2002 |
| 6461902 | RF LDMOS on partial SOI substrate In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, ... | 10/08/2002 |
| 6448105 | Method for doping one side of a semiconductor body A method for doping one side of a semiconductor substrate, such as in a silicon wafer, wherein an oxide layer is deposited on both the side to be doped and the non-doped side of the semiconductor substrate. A doping layer, containing a doping agent, is de... | 09/10/2002 |
| 6436772 | Method of manufacturing semiconductor device having memory cell transistors A plurality of diffusion layers extending in a first direction is formed at a surface of a semiconductor substrate in a cell region to be provided with the memory cell transistors. A plurality of gate electrodes extending in a second direction perpendicul... | 08/20/2002 |
| 6410378 | Method of fabrication of semiconductor structures by ion implantation The present invention relates to formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. P-type dopant are implanted into a semiconductor substrate hav... | 06/25/2002 |
| 6391733 | Method of doping semiconductor devices through a layer of dielectric material A method of making a semiconductor device includes performing a doping implant through a layer of dielectric material. The implanting through dielectric material enables use of high-energy implants to form shallow doped regions. Other implanting steps may... | 05/21/2002 |
| 6362508 | Triple layer pre-metal dielectric structure for CMOS memory devices A CMOS memory device includes source and drain regions diffused into a substrate, a polysilicon gate structure formed over a channel region located between the first and second diffusion regions, and a pre-metal dielectric structure formed over the polysi... | 03/26/2002 |
| 6303436 | Method for fabricating a type of trench mask ROM cell A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the n... | 10/16/2001 |
| 6294430 | Nitridization of the pre-ddi screen oxide A flash memory device and a method of manufacturing the flash memory device having high reliability in which a gate stack is formed on a tunnel oxide formed on a substrate and a layer of oxide is formed on the surfaces of the gate stack and exposed surfac... | 09/25/2001 |
| 6255183 | Manufacture of a semiconductor device with a MOS transistor having an LDD structure using SiGe spacers A method of manufacturing a semiconductor device with a MOS transistor having an LDD structure. A gate dielectric (6) and a gate electrode (7, 8) are formed on a surface (5) of a silicon substrate (1). The surface adjacent the gate electrode is then expos... | 07/03/2001 |
| 6184050 | Method for forming a photodiode A method for forming a photodiode is provided. A substrate having a well with a first electric type therein is provided. An insulating layer is formed on the substrate. The insulating layer is patterned to form an opening. The insulating layer still remai... | 02/06/2001 |
| 6159809 | Method for manufacturing surface channel type P-channel MOS transistor while suppressing P-type impurity penetration In a method for manufacturing a surface channel type P-channel MOS transistor, a gate insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating layer. Then, a P-type impurity diffusion preventing operat... | 12/12/2000 |
| 6153470 | Floating gate engineering to improve tunnel oxide reliability for flash memory devices A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunn... | 11/28/2000 |
| 6107169 | Method for fabricating a doped polysilicon feature in a semiconductor device In a non-volatile semiconductor memory device, a top surface of a floating gate that is made of polysilicon is advantageously kept smooth to increase the uniformity of an overlying interpoly dielectric layer onto which a control gate is formed. The floati... | 08/22/2000 |
| 6096599 | Formation of junctions by diffusion from a doped film into and through a silicide during silicidation High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the... | 08/01/2000 |
| 6093648 | Production method for a discrete structure substrate The problem to be solved by the present invention is providing a production method capable of adjusting a dislocation density freely to a required dislocation density level for a discrete structure substrate. According to the present invention, when produ... | 07/25/2000 |
| 6060745 | Semiconductor device having a monotonically decreasing impurity concentration An n- layer (2E) having a low impurity concentration is epitaxially grown on a surface (S1) of an n+ silicon substrate (1) having a high impurity concentration to a depth (D), and phosphorus ions (P) are implanted from the surface ... | 05/09/2000 |
| 6051440 | Method of fabricating a low-inductance in-line resistor for superconductor integrated circuits A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of ... | 04/18/2000 |
| 5789295 | Method of eliminating or reducing poly1 oxidation at stacked gate edge in flash EPROM process A gate stack formation process directed toward reducing floating gate oxidation which influences tunnel oxide thickness and, therefore, discharge speed. On a substrate upon which is formed an oxide layer, a first polysilicon layer, a dielectric layer, and... | 08/04/1998 |
| 5712208 | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine.... | 01/27/1998 |
| 5646073 | Process for selective deposition of polysilicon over single crystal silicon substrate and resulting product A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon ... | 07/08/1997 |
| 5629221 | Process for suppressing boron penetration in BF2+ -implanted P+ -poly-Si gate using inductively-coupled nitrogen plasma A process for suppressing boron penetration in BF2+ -implanted P+ -poly-Si gates provides a nitrided layer between the oxide layer and poly-Si through use of inductively-coupled nitrogen plasma (ICNP) to form an energy bar... | 05/13/1997 |
| 5569624 | Method for shallow junction formation A doping sequence that reduces the cost and complexity of forming source/drain regions in complementary metal oxide silicon (CMOS) integrated circuit technologies. The process combines the use of patterned excimer laser annealing, dopant-saturated spin-on... | 10/29/1996 |
