Class 438/919 - Compensation doping

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Art collection under 914 involving doping of over-lapping
No. of patents: 84
Last issue date: 08/26/2008

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Number	Title	Issue Date
7416958	Epitaxial semiconductor layer and method A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor...	08/26/2008
7172949	Epitaxial semiconductor layer and method A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor...	02/06/2007
6943116	Method for fabricating a p-channel field-effect transistor on a semiconductor substrate A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining...	09/13/2005
6777254	Semiconductor device and fabrication method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulatio...	08/17/2004
6756619	Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th...	06/29/2004
6551903	Melt through contact formation method A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a ...	04/22/2003
6534354	Method of manufacturing MOS transistor with fluorine implantation at a low energy A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in th...	03/18/2003
6455402	Method of forming retrograde doping file in twin well CMOS device The method of fabricating a semiconductor device includes the steps of selectively forming an insulating oxide layer in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate has first and second regions; forming i...	09/24/2002
6436769	Split gate flash memory with virtual ground array structure and method of fabricating the same The present invention provides a flash memory having a split gate structure and virtual ground array structure, wherein a high impurity concentration region of a first conductivity type is provided in a drain adjacent region of a channel region under a fl...	08/20/2002
6399457	Semiconductor device having capacitor and method of manufacturing the same A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2 O5 layer, and a second electrode composed of first and second metal nitride layers ...	06/04/2002
6362035	Channel stop ion implantation method for CMOS integrated circuits A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. T...	03/26/2002
6297101	Method for producing an MOS transistor structure with elevated body conductivity In a method is described for producing an MOS transistor structure with elevated body conductivity, a substrate layer is prepared and body regions are formed therein the body regions defining a main surface of the transistor structure and at least one cha...	10/02/2001
6245608	Ion implantation process for forming contact regions in semiconductor materials A method of contact ion implantation is disclosed. Only one mask and a dosage-enhanced implantation is utilized to form different types of doped contact regions. A blanket ion implantation is first carried out, and all the contact regions of first and sec...	06/12/2001
6165847	Nonvolatile semiconductor memory device and method for manufacturing the same A nonvolatile semiconductor memory device having a semiconductor substrate of a first conductive type, a floating gate and a control gate provided on the semiconductor substrate, at least a pair of impurity diffusion layers of a second conductive type def...	12/26/2000
6107137	Method of forming a capacitor A method of forming a capacitor includes, a) providing a series of alternating first and second layers of semiconductive material over a node location, a first of the first and second layers having an average conductivity enhancing dopant concentration of...	08/22/2000
6103562	Method of making semiconductor device with decreased channel width and constant threshold voltage Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a sec...	08/15/2000
6100143	Method of making a depleted poly-silicon edged MOSFET structure A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain region...	08/08/2000
6051458	Drain and source engineering for ESD-protection transistors A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode st...	04/18/2000
5976942	Method of manufacturing a high-voltage semiconductor device An epitaxial layer with a doping of approximately 1012 atoms per cm2 is used in accordance with the resurf condition for the high-voltage circuit element in high-voltage integrated circuits of the resurf type. If the circuit comprise...	11/02/1999
5943594	Method for extended ion implanter source lifetime with control mechanism A method for controlling the implantation of ions into a target. An ion source chamber having a filament for causing evolution of the ions to be implanted is provided. An ion source reactant gas is provided for providing a source of the ion species to be ...	08/24/1999
5940724	Method for extended ion implanter source lifetime The life of a source filament in an ion implantation tool is extended by providing in the ion implantation tool both an ion source reactant gas for providing a source of ion species to be implanted and a counteracting gas to counter the chemical transport...	08/17/1999
5933737	Buried-channel MOS transistor and process of producing same In fabricating a buried p-channel MOS transistor using an n-type substrate, a shallow n-type diffused layer is formed by ion implantation in each of intended source and drain regions so as to become oppositely adjacent to the shallow p-type diffused layer...	08/03/1999
5908309	Fabrication method of semiconductor device with CMOS structure A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a ...	06/01/1999
5834347	MIS type semiconductor device and method for manufacturing same A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped...	11/10/1998
5780330	Selective diffusion process for forming both n-type and p-type gates with a single masking step First and second conductivity type regions are produced in a polysilicon layer using only a single masking step. In one embodiment, the polysilicon layer is doped to a first conductivity type. A first oxide layer is then formed and patterned over the poly...	07/14/1998
5773335	Method for forming twin-tub wells in substrate A method for forming twin-tub wells in a semiconductor substrate is disclosed. The present invention includes forming a first silicon oxide layer on the substrate. A silicon nitride layer is patterned on a portion of the first silicon oxide layer by a pho...	06/30/1998
5766695	Method for reducing surface layer defects in semiconductor materials having a volatile species The number of surface defects in semiconductor materials having a volatile species, particulary group-III nitride-based semiconductor devices, are reduced by first implanting species atoms into the semiconductor sample to fill some of the surface layer sp...	06/16/1998
5756383	Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer A semiconductor device fabrication process in which an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. According to the process, a gate electrode is formed on a substrate and an active region of the substr...	05/26/1998
5661046	Method of fabricating BiCMOS device A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, a...	08/26/1997
5492847	Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets A method of processing a semiconductor device shapes a layer buried within a substrate of the semiconductor device. This layer has a conductivity the same as that of the substrate but has a higher doping level. In this process, a region of the layer is se...	02/20/1996
5482888	Method of manufacturing a low resistance, high breakdown voltage, power MOSFET A metal oxide semiconductor field effect transistor power device with a lightly doped silicon substrate includes a source region and a drain region. At least one field implanted island region is formed along the surface of the oppositely substrate between...	01/09/1996
5384279	Method of manufacturing a semiconductor device comprising a silicon body in which semiconductor regions are formed by ion implantations A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the...	01/24/1995
5374589	Process of making a bistable photoconductive component Semi-insulating gallium arsenide wafers manufactured with varying silicon nsity shallow donors are copper compensated by heating to temperature of at least 550° C. to thermally diffuse the copper into the wafers and thereby provide deep copper acceptors ...	12/20/1994
5362657	Lateral complementary heterojunction bipolar transistor and processing procedure A method of fabricating a heterojunction bipolar transistor and the transistor by providing a substrate of a group III-V semiconductor material, doping a first selected region at a surface of the substrate a predetermined first conductivity type, concurre...	11/08/1994
5278085	Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed ov...	01/11/1994
5252499	Wide band-gap semiconductors having low bipolar resistivity and method of formation A wide band-gap semiconductor, such as a II-VI semiconductor having low bipolar resistivity and a method for producing such a semiconductor. To form this semiconductor, atomic hydrogen is used to neutralize compensating contaminants. Alternatively, the se...	10/12/1993
5198370	Method for producing an infrared detector In a method of producing an infrared detector, a first conductivity type semiconductor layer, in which lattice vacancies acting as first conductivity type carriers are formed by evaporation of an element during annealing, is formed on a substrate and dopa...	03/30/1993
5185276	Method for improving low temperature current gain of bipolar transistors A method for improving the low temperature current gain of silicon bipolar transistors by implanting a first and a second impurity of the same conductivity type into the base region to provide a high doping level base that increases bandgap narrowing with...	02/09/1993
5175119	Method of producing insulated-gate field effect transistor A polysilicon layer of approximately 500Å in thickness and a PSG layer approximately 3000Å in thickness are sequentially layered on a silicon wafer on which a gate insulating layer is formed; an opening having been formed in the PSG layer. After forming...	12/29/1992
5128277	Conductivity modulation type semiconductor device and method for manufacturing the same A conductivity modulation type semiconductor device comprises a semiconductor anode substrate of a P type having two surfaces, a semiconductor substrate of an N type having two surfaces, the semiconductor substrate having a high impurity layer-like region...	07/07/1992

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Class 438/919 - Compensation doping