Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7425480 | Semiconductor device and method of manufacture thereof A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 09/16/2008 |
| 7303946 | Method of manufacturing a semiconductor device using an oxidation process A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 12/04/2007 |
| 7208325 | Refreshing wafers having low-k dielectric materials A low-k dielectric layer having a composition of silicon, oxygen and carbon is removed from a wafer. The low-k dielectric layer is removed by exposing a surface of the low-k dielectric layer to an oxygen-containing gas to oxidized the surface. The oxidized surface i... | 04/24/2007 |
| 6890832 | Radiation hardening method for shallow trench isolation in CMOS A radiation-hardened STI process includes implanting a partially formed wafer with a fairly large dose (1013 to 1017 ions/cm2) of a large atom group III element, such as B, Al, Ga or In at an energy between about 30 and 500 keV. The ... | 05/10/2005 |
| 6844225 | Self-aligned mask formed utilizing differential oxidation rates of materials A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe... | 01/18/2005 |
| 6784115 | Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin i... | 08/31/2004 |
| 6777333 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes the steps of: forming an insulating film on a conductive pattern formed on a substrate; forming a resist pattern on the insulating film; performing etching to the insulating film using the resist pattern as a ... | 08/17/2004 |
| 6759263 | Method of patterning a layer of magnetic material A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such the protected and unprotected regions are defined. The unprotected regions are oxidized to for... | 07/06/2004 |
| 6610211 | Method of processing internal surfaces of a chemical vapor deposition reactor The invention encompasses methods of processing internal surfaces of a chemical vapor deposition reactor. In one implementation, material is deposited over internal surfaces of a chemical vapor deposition reactor while processing semiconductor substrates ... | 08/26/2003 |
| 6555484 | Method for controlling the oxidation of implanted silicon Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and t... | 04/29/2003 |
| 6455440 | Method for preventing polysilicon stringer in memory device In accordance with the present invention, a method for preventing polysilicon stringers in memory devices is disclosed. The key aspect of the present invention is the formation of a floating gate structure with multi-level oxidation rates the lower portio... | 09/24/2002 |
| 6368986 | Use of selective ozone TEOS oxide to create variable thickness layers and spacers A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressu... | 04/09/2002 |
| 6344416 | Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production r... | 02/05/2002 |
| 6335288 | Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching condition... | 01/01/2002 |
| 6239478 | Semiconductor structure for a MOS transistor The MOS transistor has field plates and a subarea of the gate formed from the same polysilicon layer. A gate oxide lying underneath them is produced at the beginning of the fabrication process and it therefore exhibits particularly high quality. The polys... | 05/29/2001 |
| 6225167 | Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation re... | 05/01/2001 |
| 6211058 | Semiconductor device with multiple contact sizes A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simply the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material t... | 04/03/2001 |
| 6087243 | Method of forming trench isolation with high integrity, ultra thin gate oxide The quality of an ultra thin gate oxide film, particularly at the edges of a shallow trench isolation structure, is improved employing a double sacrificial oxide technique. After trench filling and planarization, the pad oxide layer thickness is increased... | 07/11/2000 |
| 6063670 | Gate fabrication processes for split-gate transistors A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first... | 05/16/2000 |
| 6052261 | Method for manufacturing magnetoresistance head A method for manufacturing a magnetoresistance head of the present invention comprises the steps of forming an organic film on a multilayered film constituting a magnetoresistance device, forming an upper film formed of resist or inorganic film on the org... | 04/18/2000 |
| 6043128 | Semiconductor device handling multi-level voltages A method of fabricating a multi power source semiconductor device handling multi-level voltages, comprises the steps of: forming first gate oxide layers by thermally oxidizing surfaces of the plurality of the active regions of said semiconductor substrate... | 03/28/2000 |
| 6015736 | Method and system for gate stack reoxidation control A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling... | 01/18/2000 |
| 5994216 | Method of forming a reduced size contact in a dielectric layer by using bird's beak of oxidized polysilicon to create an etching mask A method for forming a reduced size contact hole over a structure. The method comprises the steps of: forming a dielectric layer on said structure; forming a polysilicon layer on said dielectric layer; forming a silicon nitride layer on said polysilicon l... | 11/30/1999 |
| 5972757 | Method of forming a self aligned through-hole on a diffused layer The present invention relates to a semiconductor device whose through-holes are formed by self-alignment, and a method for fabricating the same. The through-holes formed on the gate electrodes can be formed simultaneously with SACs without complicating th... | 10/26/1999 |
| 5922621 | Quantum semiconductor device and a fabrication process thereof A method for fabricating a quantum semiconductor device includes the steps of forming an etch pit of a triangular pyramid on a {111}A-oriented principal surface of a substrate having zinc blende structure by a dry etching process, and depositing semicondu... | 07/13/1999 |
| 5824601 | Carboxylic acid etching solution and method A sacrificial oxide etching solution of carboxylic acid and HF having a high etch selectivity for silicon oxide relative to polysilicon, metal, and nitride. The solution is useful in the fabrication of microstructures having integrated electronics on the ... | 10/20/1998 |
| 5798303 | Etching method for use in fabrication of semiconductor devices An etching method includes providing a first surface and a second surface with the second surface lying substantially vertical to the first surface. A material is provided over at least a portion of the first and second surface. The material is anisotropi... | 08/25/1998 |
| 5707888 | Oxide formed in semiconductor substrate by implantation of substrate with a noble gas prior to oxidation A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 9... | 01/13/1998 |
| 5705027 | Method of removing etching residues The method is to selectively etch the etching residue in non-conductive state occurring in semiconductor manufacturing process. A silicon substrate cassette is used in such selective etching. In removing the etching residue in non-conductive state occurring in... | 01/06/1998 |
| 5700628 | Dry microlithography process An all-dry microlithography process, where a fluorinated layer 30 is deposited on a processable layer 18 of a semiconductor wafer, and regions of the fluorinated layer 30 are exposed to a masked radiation source so that exposed regions and unexposed areas... | 12/23/1997 |
| 5686346 | Method for enhancing field oxide thickness at field oxide perimeters A method for enhancing the thickness of a field oxide layer at perimeters of the field regions is presented. The use of a relatively thin pad oxide layer under a nitride layer reduces lateral encroachment of the field oxide layer into device active areas,... | 11/11/1997 |
| 5679600 | Double locos for submicron isolation An improved LOCOS process is provided particularly for use with submicron isolation dimensions in the form of a double LOCOS process, in which double LOCOS stacks are formed upon a silicon substrate including a thin first oxide (pad oxide) layer, a thin f... | 10/21/1997 |
| 5674776 | Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad... | 10/07/1997 |
| 5670412 | Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate A semiconductor processing method of forming field oxide regions includes, a) providing a sacrificial pad oxide layer over a semiconductor substrate; b) providing a Gex Siy layer over the pad oxide layer, where x is greater than 0.2,... | 09/23/1997 |
| 5654215 | Method for fabrication of a non-symmetrical transistor In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, a gate insulator and a gate electrode, such as a polysilicon, are formed over a semiconductor substrate, the gate electrode having a top sur... | 08/05/1997 |
| 5650351 | Method to form a capacitor having multiple pillars for advanced DRAMS A method of fabricating a capacitor having multiple pillars is presented. The invention uses an oxidized hemispherical grain silicon (HSG-Si) layer as a masking layer, in a series of masking steps, to form pillarets on a storage electrode. The method begi... | 07/22/1997 |
| 5627099 | Method of manufacturing semiconductor device In a method of manufacturing a semiconductor device, after forming a poly silicon film 54 on a surface of a silicon substrate 51, a silicon nitride film 55 is formed in accordance with a desired pattern and a local oxidation process is carried out to form... | 05/06/1997 |
| 5624861 | Method of manufacturing semiconductor device A manufacturing method of a semiconductor device includes the steps of depositing a metallic film (light-shielding film), an insulating film and a semiconductor film in this order on an insulating substrate, and after patterning the insulating film and th... | 04/29/1997 |
| 5612246 | Method for manufacturing semiconductor substrate having buck transistor and SOI transistor areas A method for manufacturing a semiconductor substrate structure wherein a comprising the steps of defining bulk transistor and SOI transistor areas, the bulk transistor area disposed on a lower single crystalline silicon layer, and the SOI transistor area ... | 03/18/1997 |
| 5595922 | Process for thickening selective gate oxide regions One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a... | 01/21/1997 |
