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| Number | Title | Issue Date |
| 6878579 | Semiconductor device and method of manufacturing the same An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconduct... | 04/12/2005 |
| 6759336 | Methods for reducing contamination of semiconductor substrates Methods for reducing contamination of semiconductor substrates after processing are provided. The methods include heating the processed substrate to remove absorbed chemical species from the substrate surface by thermal desorption. Thermal desorption can be performe... | 07/06/2004 |
| 6391805 | High-pressure anneal process for integrated circuits This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of ... | 05/21/2002 |
| 6387828 | High-pressure anneal process for integrated circuits This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of ... | 05/14/2002 |
| 6352946 | High-pressure anneal process for integrated circuits This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of ... | 03/05/2002 |
| 6187632 | Anneal technique for reducing amount of electronic trap in gate oxide film of transistor A memory cell of EEPROM having a floating gate, a control gate, a drain region, and a source region is formed on a silicon substrate. Thereafter, a BPSG film (interlayer insulating film) covering the memory cell is formed by CVD. After a wire including a ... | 02/13/2001 |
| 6184135 | Insitu formation of TiSi2/TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi2 layer The present invention provides a method of forming a contact structure comprised of: a silicon substrate, a titanium silicide layer, a barrier (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming... | 02/06/2001 |
| 5910257 | Process for producing a semiconductor device using purified phosphoric acid A process for the preparation of an analytical sample characterized by depositing and separating solely the impurity to be analyzed from phosphoric acid; a process for analysis of the impurity characterized by depositing and separating solely the impurity... | 06/08/1999 |
| 5851847 | Photonic device and process for fabricating the same A photonic device according to the present inventions obtained by resin molding a photonic element mounted on a base using a light-transmitting resin wherein the cured hardness of the light-transmitting resin is set at a value for optimally minimizing the... | 12/22/1998 |
| 5766966 | Power transistor device having ultra deep increased concentration region A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentrati... | 06/16/1998 |
| 5747371 | Method of manufacturing vertical MOSFET A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first reg... | 05/05/1998 |
| 5624852 | Manufacturing process for obtaining integrated structure bipolar transistors with controlled storage time Integrated structure bipolar transistors with controlled storage time are manufactured by forming at least one bipolar transistor occupying a first area on a first surface of the silicon material, covering the first surface of the silicon material with an... | 04/29/1997 |
| 5580795 | Fabrication method for integrated structure such as photoconductive impedance-matched infrared detector with heterojunction blocking contacts A photoconductive isotype heterojunction impedance-matched infrared detector has blocking contacts which are positioned on the bottom side of the detector. The blocking contacts prevent transfer of minority carriers from the active region of the detector,... | 12/03/1996 |
| 5468660 | Process for manufacturing an integrated bipolar power device and a fast diode A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable... | 11/21/1995 |
| 5441900 | CMOS latchup suppression by localized minority carrier lifetime reduction A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar be... | 08/15/1995 |
| 5420045 | Process for manufacturing thyristor with adjustable breakover voltage Thyristor with an npnp layer sequence, in which a zone (14) enriched with generation and recombination centers and formed by proton irradiation is provided underneath the triggering contact (7) in the n-type base (3), which enriched zone defines, by means... | 05/30/1995 |
| 5284780 | Method for increasing the electric strength of a multi-layer semiconductor component For increasing the electric strength of a semiconductor component that comprises a sequence of semiconductor layers of alternating conductivity type and which is adapted to be charged with a voltage that biases at least one of the p-n junctions that separ... | 02/08/1994 |
| 5283202 | IGBT device with platinum lifetime control having gradient or profile tailored platinum diffusion regions For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (~1014 /cm3 | 02/01/1994 |
| 5240876 | Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process An SOI wafer is formed having a silicon-germanium layer between the epitaxial layer of the device and the insulative layer. The process includes bonding a second substrate to a silicon-germanium layer on a first substrate by an intermediate insulative lay... | 08/31/1993 |
| 5227315 | Process of introduction and diffusion of platinum ions in a slice of silicon A process is provided for introduction and diffusion of platinum ions in a slice of silicon material. The slice of silicon is subjected to a succession of thermal steps at high temperature for the formation of at least one semiconductor device. Later proc... | 07/13/1993 |
| 5196354 | Method of manufacturing semiconductor device with controlled carrier lifetime A semiconductor device has a semiconductor substrate, an insulated gate field-effect transistor section formed in the substrate and a peripheral section formed in the substrate and arranged to substantially surround the field-effect transistor section. A ... | 03/23/1993 |
| 5141879 | Method of fabricating a FET having a high trap concentration interface layer A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised... | 08/25/1992 |
| 5124772 | Insulated gate bipolar transistor with a shortened carrier lifetime region In a power semiconductor device such as an IGBT, a fifth region of n conductivity type is provided. The fifth region is formed in a portion of a second region (drain region) contacting an insulating layer below the gate layer. The fifth region contacts a ... | 06/23/1992 |
| 4963509 | Gold diffusion method for semiconductor devices of high switching speed Gold is diffused into a silicon substrate by first depositing an ultrathin layer of gold on one of the main faces of the substrate and then by heating the substrate to a temperature range of about 300°-850° C., instead of to about 1000° according to ... | 10/16/1990 |
| 4925812 | Platinum diffusion process Platinum atoms are uniformly dispersed throughout a silicon wafer containing preformed junctions by depositing a layer of platinum on a clean silicon surface and thereafter immediately heating the wafer to about 500° C. to form platinum silicide. Alterna... | 05/15/1990 |
| 4903102 | Semiconductor photoelectric conversion device and method of making the same A semiconductor photoelectric conversion device is provided with a PIN structure which comprises P-type, I-type and N-type non-single-crystal semiconductor layers laminated in that order or in the reverse order. The I-type layer contains a recombination c... | 02/20/1990 |
| 4806497 | Method for producing large-area power semiconductor components A method for producing large-area power semiconductor components, wherein at least two irradiation processes (neutron irridiation, ion implantation electron, γor proton irradiation) are used to produce the basic doping, to introduce deep pn junctions and... | 02/21/1989 |
| 4792530 | Process for balancing forward and reverse characteristic of thyristors A thyristor having a beveled edge extending from its top surface is irradiated by an electron beam which is applied only to the beveled surface and is also electron beam irradiated from its bottom surface through an expansion plate fixed to the bottom sur... | 12/20/1988 |
| 4777149 | Method of manufacturing power MOSFET In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the... | 10/11/1988 |
| 4766482 | Semiconductor device and method of making the same A semiconductor device having a layer of semiconductor material disposed on an insulating substrate is disclosed. A means is provided within the insulating substrate for minimizing the collection of radiation-induced charge carriers at the interface betwe... | 08/23/1988 |
| 4710477 | Method for forming latch-up immune, multiple retrograde well high density CMOS FET A high density CMOS device structure that is essentially immune to latch-up, and a method of fabricating the structure, is described. This is obtained by providing a well region within and adjacent a surface of a substrate, the well region having a multip... | 12/01/1987 |
| 4684413 | Method for increasing the switching speed of a semiconductor device by neutron irradiation A method for decreasing the turnoff time in a crystalline semiconductor region within a semiconductor device comprises initially providing a semiconductor region having a predetermined density of pinning centers. The semiconductor region is then irradiate... | 08/04/1987 |
| 4662957 | Method of producing a gate turn-off thyristor A method of producing a gate turn-off thyristor includes producing a first n type impurity region, a second p type impurity region, a third n type impurity region, and a fourth p type impurity region produced in a semiconductor substrate providing a catho... | 05/05/1987 |
| 4613519 | Electron-beam-induced information storage in hydrogenated amorphous silicon device A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge-collection device; and generating defects in the hydrogenated amorphous silico... | 09/23/1986 |
| 4613381 | Method for fabricating a thyristor In a method for fabricating a thyristor in which n-type impurities are diffused in a p-base of a pnp wafer to form an n+ -emitter, the step of diffusing the n-type impurities for forming the n+ -emitter has the conditions which are s... | 09/23/1986 |
| 4585489 | Method of controlling lifetime of minority carriers by electron beam irradiation through semi-insulating layer A semiconductor device and a method of manufacturing the same are disclosed wherein a semi-insulating film having a high trap density is formed on a semiconductor substrate so as to prevent charges from remaining in the semi-insulating film and to prevent... | 04/29/1986 |
| 4402001 | Semiconductor element capable of withstanding high voltage A semiconductor element such as a thyristor or a transistor which is capable of withstanding a high voltage comprises a semiconductor substrate of a pnpn-four layer structure (for a thyristor) or of a npn-three layer structure (for a transistor). An inter... | 08/30/1983 |
| 4398054 | Compensated amorphous silicon solar cell incorporating an insulating layer A P-I-N type compensated amorphous silicon solar cell which incorporates an insulating layer adjacent to the compensated intrinsic amorphous silicon layer.... | 08/09/1983 |
| 4370180 | Method for manufacturing power switching devices A method for manufacturing power switching devices such as thyristors and power transistors comprising the steps of forming impurity diffused layers of one conductivity type and of the opposite conductivity type in a semiconductor substrate of one conduct... | 01/25/1983 |
| 4301323 | Lead-doped silicon with enhanced semiconductor properties Silicon having semiconductor properties, adapted for use as an optoelectronic component, in particular solar cells, has its optoelectronic properties improved by adding to the silicon an agent, preferably lead, which increases the carrier life time.... | 11/17/1981 |
