Class 438/901 - CAPACITIVE JUNCTION

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Art collection involving the construction of a barrier layer
No. of patents: 28
Last issue date: 12/18/2007

Number	Title	Issue Date
7309875	Nanocrystal protective layer for crossbar molecular electronic devices A molecular device is provided. The molecular device comprises a junction formed by a pair of crossed electrodes where a first electrode is crossed by a second electrode at a non-zero angle and at least one connector species including at least one switchable moiety ...	12/18/2007
7285460	Semiconductor device and method of manufacturing the same There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric...	10/23/2007
7033900	Protection of integrated circuit gates during metallization processes In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup...	04/25/2006
6949477	Method of fabricating a capacitive element for a semiconductor device A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrat...	09/27/2005
6143614	Monolithic inductor The monolithic inductor (30) includes a substrate (38), a spiral metal trace (32) disposed insulatively above the substrate (38), where a parasitic capacitance (56) is generated between the spiral metal trace (32) and the substrate (38), and a depletion l...	11/07/2000
5843829	Method for fabricating a semiconductor device including a step for forming an amorphous silicon layer followed by a crystallization thereof A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer wi...	12/01/1998
5554552	PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant i...	09/10/1996
5519243	Semiconductor device and manufacturing method thereof A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the p...	05/21/1996
5492856	Method of forming a semiconductor device having a LC element An LC element with a pn junction layer formed near the surface of a p-Si substrate by forming an n+ region having a predetermined shape and in a portion thereof additionally forming a p+ region having the same shape, and with first...	02/20/1996
5338691	Method of making a photodiode with reduced junction area The present invention discloses a light-receiving element, and method for making same, for a charge storage light sensor having a first semiconductor later of a first conductive type with an element isolation region disposed thereon. The element isolation...	08/16/1994
5334547	Method of manufacturing a semiconductor memory having an increased cell capacitance in a restricted cell area A semiconductor memory includes at least one memory cell composed of an insulated gate field effect transistor and an associated stacked capacitor which are formed close to each other on a single substrate of a first conduction type. The insulated gate fi...	08/02/1994
5262353	Process for forming a structure which electrically shields conductors A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is e...	11/16/1993
5182223	Method of making an integrated circuit with capacitor An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccu...	01/26/1993
5162264	Integrated circuit package Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is impleme...	11/10/1992
5135889	Method for forming a shielding structure for decoupling signal traces in a semiconductor A method for forming a semiconductor structure including parallel spaced conducting traces each physically separated by a grounding trace. The grounding traces are located in between the conducting traces to provide a shielding structure to diminish capac...	08/04/1992
5053352	Method of forming an integrated circuit with pn-junction capacitor In a method of forming an integrated circuit array having a capacitance formed by a pn-junction and separated from other components by a pn-junction, semiconductor areas are provided which connect that zone of the two semiconductor zones forming the pn-ju...	10/01/1991
4999309	Aluminum-implant leakage reduction An improved process is described for the formation of PNP transistor collector base junctions or PN junction capaciters in silicon monolithic integrated circuits that employ the ion implantation and diffusion of aluminum in these regions that are to conta...	03/12/1991
4853348	Process for manufacture of a semiconductor memory device A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large...	08/01/1989
4505766	Method of fabricating a semiconductor device utilizing simultaneous outdiffusion and epitaxial deposition A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is...	03/19/1985
4476623	Method of fabricating a bipolar dynamic memory cell This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP t...	10/16/1984
4427457	Method of making depthwise-oriented integrated circuit capacitors A depthwise-oriented capacitor comprises a cluster of separate, parallel, narrow elongated oppositely-doped conductive regions extending depthwise into a semiconductor substrate, for example, in an integrated circuit. The conductive regions can be paralle...	01/24/1984
4326332	Method of making a high density V-MOS memory array A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Ho...	04/27/1982
4314359	Semiconductor memory device The invention relates to an improvement in a semiconductor memory device including flip-flop type memory cells, each memory cell consisting of a pair of cross-coupled multi-emitter transistors. The semiconductor memory device of the invention is character...	02/02/1982
4227297	Method for producing a single transistor storage cell For the production of V-MOS single transistor storage cells at the surface of a silicon crystal of first conductivity type, two adjoining zones of opposite conductivity type can first be produced by masked diffusion or implantation. Then, with the use of ...	10/14/1980
4222816	Method for reducing parasitic capacitance in integrated circuit structures A method for reducing parasitic capacitance in semiconductor devices, particularly for the removal of raised portions of conductive layers overlying and capable of being capacitively coupled to other conductors in semiconductor memory integrated circuits....	09/16/1980
4194283	Process for the production of a single transistor memory cell In the production of V-MOS single transistor memory cells a simplification of the previous technology is disclosed wherein a process is utilized without epitaxial processes and with a minimum of doping processes. First the source and the drain zone of a f...	03/25/1980
4116720	Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silico...	09/26/1978
3975818	Method of forming closely spaced electrodes onto semiconductor device A method of forming at least two electrodes of a portion of a semiconductor device, the portion including one or more semiconductor regions and being covered with an insulating protective film, comprises the steps of providing a hole for the first electro...	08/24/1976

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Class 438/901 - CAPACITIVE JUNCTION