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| Number | Title | Issue Date |
| 7135412 | Method to control a management system to control semiconductor manufacturing equipment In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the etching process is recognized. It is checked whether the information of ... | 11/14/2006 |
| 7132306 | Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set A method of forming an interlevel dielectric (ILD) layer forms a polymer sacrificial ILD on a substrate. After metallization structures are formed in the polymer sacrificial ILD layer, a low power etch back is performed on the sacrificial ILD layer. Dielectric mater... | 11/07/2006 |
| 7131391 | Plasma reaction chamber liner comprising ruthenium The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or more elements selected from Group VIII of the periodic table is provided within a reaction chamber; and a ... | 11/07/2006 |
| 7132618 | MERIE plasma reactor with overhead RF electrode tuned to the plasma with arcing suppression A plasma reactor for processing a semiconductor workpiece, includes reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supp... | 11/07/2006 |
| 7128803 | Integration of sensor based metrology into semiconductor processing tools A system for processing a wafer is provided. The system includes a chemical mechanical planarization (CMP) tool. The CMP tool includes a wafer carrier defined within a housing. A carrier film is affixed to the bottom surface and supports a wafer. A sensor embedded i... | 10/31/2006 |
| 7129178 | Reducing defect formation within an etched semiconductor topography A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an e... | 10/31/2006 |
| 7129179 | Method for topographical patterning of a device The device of the present invention facilitates engaging mating elements, such as actuators used in disc drives, with a pattern on the device. The improved device includes arcuate edges between at least one of the sidewalls in the pattern and the surface of the devi... | 10/31/2006 |
| 7125804 | Etching methods and apparatus and substrate assemblies produced therewith Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed ... | 10/24/2006 |
| 7125792 | Dual damascene structure and method A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions havi... | 10/24/2006 |
| 7125806 | Etching method An etching method comprises a step of forming a via hole structure based on a photoresist film layer (210) for forming a wiring pattern, a silicon oxide film layer (201) which is a hard mask layer formed under the photoresist film, and an organic Low-k... | 10/24/2006 |
| 7122850 | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor... | 10/17/2006 |
| 7122478 | Method of manufacturing a semiconductor device using a polysilicon etching mask A method of manufacturing a semiconductor device using a polysilicon layer as an etching mask includes: (a) forming an interlayer dielectric over a semiconductor substrate; (b) forming a polysilicon layer pattern over the interlayer dielectric; (c) forming a contact... | 10/17/2006 |
| 7122480 | Method of plasma etching a substrate A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high powe... | 10/17/2006 |
| 7122479 | Etching processing method An etching processing method capable of etching a low dielectric constant layer at a reduced cost by using an etching processing apparatus comprising a vacuum vessel, a sample loading electrode disposed in the vacuum vessel, a gas introduction device for introducing... | 10/17/2006 |
| 7118683 | Methods of etching silicon-oxide-containing compositions The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or more elements selected from Group VIII of the periodic table is provided within a reaction chamber; and a ... | 10/10/2006 |
| 7119013 | Method for fabricating semiconductor device with fine patterns A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive struc... | 10/10/2006 |
| 7115926 | Capacitor constructions, DRAM constructions, and semiconductive material assemblies In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching ... | 10/03/2006 |
| 7115484 | Method of dicing a wafer A method of dicing a wafer is disclosed. A wafer with an active surface and a back surface is provided. Prior to dicing the wafer, a removable layer is formed on the back surface of the wafer. The removable layer is attached to a tape, such as a sawing tape. After t... | 10/03/2006 |
| 7115519 | Method for plasma treatment A method for plasma treatment etches an SiC layer with an increased etching rate and enhanced selectivities of SiC with respect to SiO2 and an organic layer. An etching gas is converted into plasma to etch SiC. The etching gas may include CHF3;... | 10/03/2006 |
| 7115523 | Method and apparatus for etching photomasks A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the ... | 10/03/2006 |
| 7112288 | Methods for inspection sample preparation Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope. ... | 09/26/2006 |
| 7111629 | Method for cleaning substrate surface There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 | 09/26/2006 |
| 7112533 | Plasma etching system and method A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma etching process so as to reduce accumulated charge on the surface of the semiconductor device during plasma et... | 09/26/2006 |
| 7112536 | Plasma processing system and method A plasma processing system and method wherein a power source produces a magnetic field and an electric field, and a window disposed between the power source and an interior of a plasma chamber couples the magnetic field into the plasma chamber thereby to couple powe... | 09/26/2006 |
| 7112795 | Method of controlling metallic layer etching process and regenerating etchant for metallic layer etching process based on near infrared spectrometer In a method of controlling a metallic layer etching process for fabricating a semiconductor device or a liquid crystal display device, the composition of the etchant used in etching the metallic layer is first analyzed with the NIR spectrometer. The state of the etc... | 09/26/2006 |
| 7112834 | Gate etch process A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitri... | 09/26/2006 |
| 7109557 | Sacrificial dielectric planarization layer A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrific... | 09/19/2006 |
| 7109098 | Semiconductor junction formation process including low temperature plasma deposition of an optical absorption layer and high speed optical annealing A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the w... | 09/19/2006 |
| 7109122 | Method and apparatus for reducing substrate charging damage The present invention presents a method and apparatus for reducing charging damage to a substrate is described. In particular, a method of operating a plasma processing system is described that leads to the removal of, or significant reduction of, the accumulated ch... | 09/19/2006 |
| 7105442 | Ashable layers for reducing critical dimensions of integrated circuit features A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited ... | 09/12/2006 |
| 7105454 | Use of ammonia for etching organic low-k dielectrics Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The di... | 09/12/2006 |
| 7105100 | System and method for gas distribution in a dry etch process A system and method for distributing gas to a substrate in a dry etch chamber make use of different flow channels to distribute the gas to different portions of a substrate. A first flow channel can be oriented to distribute gas to an inner portion of the substrate.... | 09/12/2006 |
| 7105102 | Vacuum plasma processor having a chamber with electrodes and a coil for plasma excitation and method of operating same A vacuum plasma processor includes a roof structure including a dielectric window carrying (1) a semiconductor plate having a high electric conductivity so it functions as an electrode, (2) a hollow coil and (3) at least one electric shield. The shield, coil and sem... | 09/12/2006 |
| 7105361 | Method of etching a magnetic material A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such that the protected and unprotected regions are defined. The unprotected regions are etched in ... | 09/12/2006 |
| 7105101 | Method of removing oxide film on a substrate with hydrogen and fluorine radicals A dry cleaning process for removing native oxide at improved efficiency is disclosed. The dry cleaning process minimizes the amount of fluorine atoms absorbed on the surface of a processed substrate. Fluorine radicals are provided to the substrate together with hydr... | 09/12/2006 |
| 7105460 | Nitrogen-free dielectric anti-reflective coating and hardmask Methods are provided for depositing a dielectric material. The dielectric material may be used for an anti-reflective coating or as a hardmask. In one aspect, a method is provided for processing a substrate including introducing a processing gas comprising a silane-... | 09/12/2006 |
| 7102235 | Conformal lining layers for damascene metallization Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Trenches and contact vias are formed in insulating layers. The trenches and vias are exposed to alternating chemistries to form monolayers of a desired linin... | 09/05/2006 |
| 7101786 | Method for forming a metal line in a semiconductor device Provided is a method for forming a metal line in a semiconductor device. The method forms round portions at top edges of an insulation film by means of a polymer and then etches the rest portion (i.e., sidewall parts) in an almost vertical direction, which makes it ... | 09/05/2006 |
| 7102146 | Dose cup located near bend in final energy filter of serial implanter for closed loop dose control An ion implantation system having a dose cup located near a final energy bend of a scanned or ribbon-like ion beam of a serial ion implanter for providing an accurate ion current measurement associated with the dose of a workpiece or wafer. The system comprises an i... | 09/05/2006 |
| 7097779 | Processing system and method for chemically treating a TERA layer A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chem... | 08/29/2006 |
