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| Number | Title | Issue Date |
| 8445387 | Epitaxial silicon growth Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the... | 05/21/2013 |
| 8426313 | Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference Methods for fabricating sublithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. ... | 04/23/2013 |
| 8383518 | Method for forming contact holes A method for forming contact holes is applied in a transistor array substrate. The transistor array substrate includes first contact pads, second contact pads located over the first contact pads, a first insulation layer covering the first contact pads, and a second... | 02/26/2013 |
| 8383517 | Substrate processing method and substrate processing apparatus A substrate processing method that can selectively remove deposit produced through dry etching of silicon. A substrate has a silicon base material and a hard mask that is made of a silicon nitride film and/or a silicon oxide film and formed on the silicon base mater... | 02/26/2013 |
| 8338305 | Multi-fin device by self-aligned castle fin formation The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening havin... | 12/25/2012 |
| 8324107 | Method for forming high density patterns Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isol... | 12/04/2012 |
| 8318603 | Method of forming patterns for semiconductor device Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second... | 11/27/2012 |
| 8314032 | Semiconductor device and method for manufacturing the same A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the subst... | 11/20/2012 |
| 8304348 | Semiconductor device manufacturing method and semiconductor device A semiconductor device manufacturing method includes: stacking a plurality of electrode layers containing a semiconductor alternately with insulating layers; processing part of a multilayer body of the electrode layers and the insulating layers into a staircase shap... | 11/06/2012 |
| 8278221 | Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced fr... | 10/02/2012 |
| 8273664 | Method for etching and filling deep trenches A method of etching and tilling deep trenches is disclosed, which includes: forming an ONO(oxide-nitride-oxide) sandwich layer on a semiconductor substrate; forming deep trenches by using top oxide of the sandwich layer as a stop layer; removing the top oxide and mi... | 09/25/2012 |
| 8252693 | Self-alignment for semiconductor patterns Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical tra... | 08/28/2012 |
| 8247329 | Nanotube semiconductor devices A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin e... | 08/21/2012 |
| 8242023 | Method of producing a semiconductor device having a trench filled with an epitaxially grown semiconductor layer A method of producing a device includes embedding trenches with an epitaxial layer having high crystallinity while a mask oxide film remains unremoved. An n-type semiconductor is formed on the surface of a silicon substrate, and a mask oxide film and a mask nitride ... | 08/14/2012 |
| 8236699 | Contact patterning method with transition etch feedback A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of ox... | 08/07/2012 |
| 8236698 | Method for forming non-aligned microcavities of different depths The invention relates to a method for forming microcavities (118) of different depths in a layer (102) based on at least an amorphous or monocrystalline material, comprising at least the following steps in which: at least one shaft and/or trench is for... | 08/07/2012 |
| 8222148 | Method of manufacturing a semiconductor device A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the se... | 07/17/2012 |
| 8222149 | Method for photoresist pattern removal The present disclosure provides a method for making a semiconductor device. The method includes forming a sacrificial layer on a substrate; forming a patterned resist layer on the sacrificial layer; performing an ion implantation to the substrate; applying a first w... | 07/17/2012 |
| 8222150 | Method of manufacturing semiconductor device, template, and method of creating pattern inspection data A method of manufacturing a semiconductor device according to an embodiment of the present invention includes mask layer on a processing target, pressing a template having a pattern having closed loop structure against the mask layer via an imprint material to solid... | 07/17/2012 |
| 8211804 | Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the... | 07/03/2012 |
| 8202803 | Method to remove capping layer of insulation dielectric in interconnect structures A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process. ... | 06/19/2012 |
| 8198194 | Methods of forming p-channel field effect transistors having SiGe source/drain regions Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrifi... | 06/12/2012 |
| 8193095 | Method for forming silicon trench A method for forming a silicon trench, comprises the steps of: defining an etching area at a silicon substrate; forming metal catalysts at the surface of the etching area; immersing the silicon substrate in a first etching solution thereby forming anisotropic silico... | 06/05/2012 |
| 8183160 | Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the expo... | 05/22/2012 |
| 8168543 | Methods of forming a layer for barrier applications in an interconnect structure Methods of forming a barrier layer are provided. In one embodiment, the method includes providing a substrate into a physical vapor deposition (PVD) chamber, supplying at least two reactive gases and an inert gas into the PVD chamber, sputtering a source material fr... | 05/01/2012 |
| 8143168 | Etching method and manufacturing method of semiconductor device The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device compris... | 03/27/2012 |
| 8124533 | Method of manufacturing power semiconductor device A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having th... | 02/28/2012 |
| 8114778 | Method of forming minute patterns in semiconductor device using double patterning A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between... | 02/14/2012 |
| 8114779 | Silicon dioxide cantilever support and method for silicon etched structures An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for ... | 02/14/2012 |
| 8097539 | Imprint mask manufacturing method for nanoimprinting A pattern is formed on a mask substrate. Positional deviation information between an actual position of the pattern formed on the mask substrate and a design position decided at the time of designing the pattern is calculated. A heterogeneous layer of which a volume... | 01/17/2012 |
| 8093152 | Trench forming method A trench forming method for forming trenches without creating gouges at the boundary between a masking oxide film and a semiconductor layer and at the boundary between an oxide film insulating layer and the semiconductor layer, includes at least three etching steps ... | 01/10/2012 |
| 8084365 | Method of manufacturing a nano structure by etching, using a substrate containing silicon A method of manufacturing a nano structure by etching, using a substrate containing Si. A focused Ga ion or In ion beam is irradiated on the surface of the substrate containing Si. The Ga ions or the In ions are injected while sputtering away the surface of the subs... | 12/27/2011 |
| 8071481 | Method for forming highly strained source/drain trenches A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a ... | 12/06/2011 |
| 8058176 | Methods of patterning insulating layers using etching techniques that compensate for etch rate variations Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically in... | 11/15/2011 |
| 8053369 | Process for forming opening portion in interlayer insulation film on metallic layer of semiconductor device A manufacturing method for a semiconductor device, including: forming a metallic layer and an interlayer insulation film on a semiconductor substrate sequentially; etching on the interlayer insulation film using fluorine-based etching gas to form an opening portion ... | 11/08/2011 |
| 8039401 | Structure and method for forming hybrid substrate A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selecti... | 10/18/2011 |
| 8034719 | Method of fabricating high aspect ratio metal structures To fabricate high aspect ratio metal structures, a two-layer structure is provided on a conductive layer. The two-layer structure includes a first layer adjacent the conductive layer and a second layer adjacent the first layer where the second layer is etchable by a... | 10/11/2011 |
| 8030215 | Method for creating ultra-high-density holes and metallization Methods and apparatuses directed to high density holes and metallization are described herein. A method may include providing a dielectric layer including a plurality of holes, forming a fill material over a top surface of the dielectric layer and in the plurality o... | 10/04/2011 |
| 8026177 | Silicon dioxide cantilever support and method for silicon etched structures A semiconductor device includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of et... | 09/27/2011 |
| 8021984 | Method for manufacturing semiconductor A method for manufacturing a semiconductor includes forming an active region for an ESD device, an active region for a first polygate and the semiconductor, and a second polygate having a form of a blanket trench on a substrate, forming an interlayer dielectric laye... | 09/20/2011 |