Bizarre Patents
A coffin, for allowing inclination for display of a deceased person in a natural position.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8008205 | Methods for producing a semiconductor device having planarization films A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of for... | 08/30/2011 |
| 7985684 | Actuating transistor including reduced channel length A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is ... | 07/26/2011 |
| 7968468 | Substrate treatment apparatus and substrate treatment method In a substrate treatment method for supplying a coating solution to a substrate with projections and depressions on a front surface thereof to form a coating film on the front surface of the substrate, the coating solution is supplied to the rotating substrate to fo... | 06/28/2011 |
| 7855148 | Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction pr... | 12/21/2010 |
| 7799690 | Method for fabricating semiconductor integrated circuit device A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vic... | 09/21/2010 |
| 7709390 | Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction pr... | 05/04/2010 |
| 7435683 | Apparatus and method for selectively recessing spacers on multi-gate devices Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed. ... | 10/14/2008 |
| 7432120 | Method for realizing a hosting structure of nanometric elements Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the b... | 10/07/2008 |
| 7425508 | Liquid crystal display device and fabricating method thereof, and thin film patterning method applied thereto A liquid crystal display device, including: a gate line on a substrate; a data line crossing the gate line with a gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern w... | 09/16/2008 |
| 7410863 | Methods of forming and using memory cell structures A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator... | 08/12/2008 |
| 7390743 | Methods for forming a structured tungsten layer and forming a semiconductor device using the same A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A second tungsten layer is formed on the first tungsten layer with a chemi... | 06/24/2008 |
| 7384799 | Method to avoid amorphous-si damage during wet stripping processes in the manufacture of MEMS devices A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent str... | 06/10/2008 |
| 7375012 | Method of forming multilayer film This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film. ... | 05/20/2008 |
| 7364997 | Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et... | 04/29/2008 |
| 7354523 | Methods for sidewall etching and etching during filling of a trench A method for sidewall etching includes providing a substrate having a trench defined therein, with the trench having fill material disposed over a bottom thereof, along a sidewall thereof, and at the trench opening. The fill material along the sidewall of the trench... | 04/08/2008 |
| 7339223 | Semiconductor devices having dual capping layer patterns and methods of manufacturing the same Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked ther... | 03/04/2008 |
| 7326657 | Post-deposition treatment to enhance properties of Si-O-C low k films A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally tak... | 02/05/2008 |
| 7300886 | Interlayer dielectric for charge loss improvement A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and ... | 11/27/2007 |
| 7300595 | Method for filling concave portions of concavo-convex pattern and method for manufacturing magnetic recording medium A method for filling concave portions of a concavo-convex pattern by which the concave portions of the concavo-convex pattern can be filled to flatten the surface with reliability, and a method for manufacturing a magnetic recording medium by which a magnetic record... | 11/27/2007 |
| 7294404 | Graded photocatalytic coatings The invention provides graded photocatalytic coatings. In one aspect, the invention provides a substrate carrying a photocatalytic coating that includes a first graded film region and a second graded film region. The first graded film region has a substantially cont... | 11/13/2007 |
| 7294578 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 11/13/2007 |
| 7285449 | Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source /drain and semiconductor device manufactured by the method A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electro... | 10/23/2007 |
| 7273783 | Methods for reducing void formation in semiconductor devices A method of forming a semiconductor device includes forming an insulating layer on a semiconductor substrate. The insulating layer has a trench therein with opposing sidewalls and a bottom surface. A first conductive layer is formed on the sidewalls and on the botto... | 09/25/2007 |
| 7268075 | Method to reduce the copper line roughness for increased electrical conductivity of narrow interconnects (<100nm) Embodiments of the present invention provide methods to reduce the copper line roughness for increased electrical conductivity in narrow interconnects having a width of less than 100 nm. These methods reduce the copper line roughness by first smoothing the surface o... | 09/11/2007 |
| 7253112 | Dual damascene process A method of fabricating semiconductor devices using dual damascene processes to form plugs in the via holes composed of various high etch materials and bottom anti-reflection coating (BARC) materials. After via hole etch, a layer of high etch rate plug material is s... | 08/07/2007 |
| 7247569 | Ultra-thin Si MOSFET device structure and method of manufacture The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a ... | 07/24/2007 |
| 7227244 | Integrated low k dielectrics and etch stops A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition condi... | 06/05/2007 |
| 7220670 | Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process. ... | 05/22/2007 |
| 7179757 | Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the pl... | 02/20/2007 |
| 7180706 | Magnetic heads and semiconductor devices and surface planarization processes for the fabrication thereof A magnetic head according to one embodiment includes a pole piece made of a magnetic material; one or more magnetic pedestals formed over the pole piece; an insulator material formed over the pole piece adjacent the magnetic pedestals; and one or more polymer layers... | 02/20/2007 |
| 7176123 | Method for manufacturing metal line of semiconductor device The present invention discloses methods for manufacturing a metal line of a semiconductor device that can prevent undesirable etching of an edge of an interlayer insulating film. In accordance with the method, a lower metal line exposed by a via contact hole is cove... | 02/13/2007 |
| 7170175 | Semiconductor device and production method thereof A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on ... | 01/30/2007 |
| 7166534 | Method of dry cleaning photoresist strips after via contact etching Semiconductor manufacturing processes that reduce production costs as well as increase throughput by substituting the PR strip and ACT wet cleaning procedure after the via contact etching of a semiconductor with dry cleaning to be performed while removing a photores... | 01/23/2007 |
| 7144749 | Method of etching a semiconductor device A method for etching windows 40 in a semiconductor device 10 having a metal fuse 14 embedded therein is disclosed. The method is for allowing accurate fuse blowing, in particular laser fuse blowing. The method involves the controlled removal of ... | 12/05/2006 |
| 7125645 | Composite photoresist for pattern transferring A composite photoresist structure includes an first organic layer located on a substrate, a sacrificial layer located on the first organic layer, and a second organic layer located on the sacrificial layer. The first organic layer is made of materials that can be ea... | 10/24/2006 |
| 7112458 | Method of forming a liquid crystal display An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a c... | 09/26/2006 |
| 7084059 | CMP system for metal deposition A system for dished metal redevelopment by providing a metal deposition solution at an interface between a moving semiconductor wafer and a moving polishing pad, which deposits metal onto dished metal in trenches in a layer of an interlayer dielectric; and by polish... | 08/01/2006 |
| 7078312 | Method for controlling etch process repeatability Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries which include hydrogen that can effectively fill high aspect ratio (typ... | 07/18/2006 |
| 7071129 | Enhancing adhesion of silicon nitride films to carbon-containing oxide films Adhesion between silicon nitride etch-stop layers and carbon doped oxide films may be improved by using plasma argon densification treatments of the carbon doped oxide films. The resulting surface layer of the carbon doped oxide films may be carbon-depleted and may ... | 07/04/2006 |
| 7071104 | Laser alignment target A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar ... | 07/04/2006 |
