Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7195932 | Enhancement of grain structure for tungsten contracts A method for enhancing grain structure of a contact material for a semiconductor device is provided. The method initiates with exposing the contact material of a contact at a first depth within the semiconductor device. Then, the exposed contact material at the firs... | 03/27/2007 |
| 7192495 | Intermediate anneal for metal deposition The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process comprises forming a plurality of recesses in or on the substrate, wherein the plurality of recesses inclu... | 03/20/2007 |
| 7192866 | Source alternating MOCVD processes to deposit tungsten nitride thin films as barrier layers for MOCVD copper interconnects An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may ... | 03/20/2007 |
| 7192845 | Method of reducing alignment measurement errors between device layers An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on... | 03/20/2007 |
| 7192892 | Atomic layer deposited dielectric layers An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate sur... | 03/20/2007 |
| 7192856 | Forming dual metal complementary metal oxide semiconductor integrated circuits Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches ma... | 03/20/2007 |
| 7193327 | Barrier structure for semiconductor devices An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier... | 03/20/2007 |
| 7192855 | PECVD nitride film A method for forming a semiconductor device is provided. In accordance with the method, a substrate (103) is provided, and a dielectric material (123) is formed on the substrate through plasma enhanced chemical vapor deposition (PECVD). The PECVD is co... | 03/20/2007 |
| 7190043 | Techniques to create low K ILD for beol One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l... | 03/13/2007 |
| 7190077 | Semiconductor structure integrated under a pad An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal e... | 03/13/2007 |
| 7189638 | Method for manufacturing metal structure using trench A method for manufacturing a metal structure using a trench includes etching a semiconductor substrate to form a trench, depositing a seed layer over the semiconductor substrate including in the trench, stacking an insulating layer over the seed layer, removing a po... | 03/13/2007 |
| 7190079 | Selective capping of copper wiring Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during el... | 03/13/2007 |
| 7189613 | Method and structure for metal-insulator-metal capacitor based memory device A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is for... | 03/13/2007 |
| 7189628 | Fabrication of trenches with multiple depths on the same substrate Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches an... | 03/13/2007 |
| 7189650 | Method and apparatus for copper film quality enhancement with two-step deposition The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for... | 03/13/2007 |
| 7189647 | Sequential station tool for wet processing of semiconductor wafers Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wa... | 03/13/2007 |
| 7188630 | Method to passivate conductive surfaces during semiconductor processing A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cle... | 03/13/2007 |
| 7186648 | Barrier first method for single damascene trench applications Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features ... | 03/06/2007 |
| 7186643 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated cir... | 03/06/2007 |
| 7186652 | Method for preventing Cu contamination and oxidation in semiconductor device manufacturing A method for reducing or preventing contamination or oxidation of copper surfaces included in semiconductor process wafers including providing a semiconductor wafer including copper features having newly formed process surfaces following a semiconductor manufacturin... | 03/06/2007 |
| 7187080 | Semiconductor device with a conductive layer including a copper layer with a dopant A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (202), forming a dielectric layer (204) over the semiconductor substrate (202), and etching a trench or a via (206) in the dielectr... | 03/06/2007 |
| 7186642 | Low temperature nitride used as Cu barrier layer A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing ... | 03/06/2007 |
| 7186636 | Nickel bonding cap over copper metalized bondpads A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the surface of the nickel cap, may be controlled. The phosphorous content of the surface of the nickel cap is sui... | 03/06/2007 |
| 7187084 | Damascene method employing composite etch stop layer A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a composite etch stop layer over the lower intermetal dielectric layer and... | 03/06/2007 |
| 7186640 | Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower ... | 03/06/2007 |
| 7186644 | Methods for preventing copper oxidation in a dual damascene process Methods of preventing oxidation of a copper interconnect of a semiconductor device are disclosed. An example method forms a lower copper interconnect on a substrate having at least one predetermined structure, deposits a nitride layer on the lower copper interconnec... | 03/06/2007 |
| 7186348 | Method for fabricating a pole tip in a magnetic transducer A method for fabricating a magnetic head with a trapezoidal shaped pole piece tip is described. The body of the main pole piece is deposited, then one or more layers for the pole piece tip are deposited. A bed material is deposited over the pole piece tip material. ... | 03/06/2007 |
| 7183206 | Fabrication of semiconductor devices Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked l... | 02/27/2007 |
| 7183180 | Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semico... | 02/27/2007 |
| 7183183 | Method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall o... | 02/27/2007 |
| 7183195 | Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention impro... | 02/27/2007 |
| 7183209 | Semiconductor device and manufacturing method thereof The semiconductor device fabrication method of the present invention includes forming metal wirings on a semiconductor substrate, forming a first blocking layer on the semiconductor substrate and the metal wiring, forming a first FSG on the first blocking layer, for... | 02/27/2007 |
| 7183201 | Selective etching of organosilicate films over silicon oxide stop etch layers A method of selectively etching organosilicate layers in integrated circuit fabrication processes is disclosed. The organosilicate layers are selectively etched using a hydrogen-containing fluorocarbon gas. The hydrogen-containing fluorocarbon gas may be used to sel... | 02/27/2007 |
| 7183203 | Method of plating a metal or metal compound on a semiconductor substrate that includes using the same main component in both plating and etching solutions A method of forming a copper oxide film including forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surf... | 02/27/2007 |
| 7179743 | Titanium underlayer for lines in semiconductor devices A thin Titanium underlayer 22 is included beneath a Titanium rich Titanium Nitride layer 28 in a metal line 20 on a silicon substrate to reduce stress voiding. ... | 02/20/2007 |
| 7180193 | Via recess in underlying conductive line A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the ... | 02/20/2007 |
| 7179742 | Interconnect circuitry, multichip module, and methods for making them Methods of electroless plating metal on a dielectric material includes dipping the dielectric in a solution containing attractive catalytic metal particles and a metal salt solution. A thicker metallic layer can be deposited on top of the resulting layer by electrop... | 02/20/2007 |
| 7179732 | Interconnection structure and fabrication method thereof An interconnection structure and a fabrication method thereof. A first organic low-k material layer, a stress redistribution layer, a second organic low-k dielectric layer are formed in sequence over a substrate, followed by forming an opening in the first organic l... | 02/20/2007 |
| 7176142 | Method of manufacturing trench structure for device A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing ... | 02/13/2007 |
| 7176121 | Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A... | 02/13/2007 |
