Class 438/687 - Copper of copper alloy conductor

Subclass of Class 438 - Semiconductor device manufacturing: process
Definition: Processes for forming a contact using copper (Cu) or an
No. of patents: 1893
Last issue date: 05/01/2012

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Number	Title	Issue Date
8168540	Methods and apparatus for depositing copper on tungsten Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and compl...	05/01/2012
8163649	Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The intercon...	04/24/2012
8158520	Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices An integrated circuit device structure with a novel contact feature. The structure includes a substrate, a dielectric layer overlying the substrate, and a metal interconnect overlying the dielectric layer. A first interlayer dielectric layer is formed surrounding th...	04/17/2012
8153524	Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemic...	04/10/2012
8143162	Interconnect structure having a silicide/germanide cap layer An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, an...	03/27/2012
8133813	Semiconductor device with a barrier film A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, formi...	03/13/2012
8133812	Methods and systems for barrier layer surface passivation This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method incl...	03/13/2012
8124532	Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous am...	02/28/2012
8043968	Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The...	10/25/2011
8039395	Technique for forming embedded metal lines having increased resistance against stress-induced material transport An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by ...	10/18/2011
8017523	Deposition of doped copper seed layers having improved reliability Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embo...	09/13/2011
8017522	Mechanically robust metal/low-κ interconnects A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrat...	09/13/2011
8008200	Poison-free and low ULK damage integration scheme for damascene interconnects A method of forming a dual damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using a tri-...	08/30/2011
8008199	Microstructure modification in copper interconnect structure Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries conf...	08/30/2011
8008198	Large scale method and furnace system for selenization of thin film photovoltaic materials A method for fabricating a copper indium diselenide semiconductor film is provided using substrates having a copper and indium composite structure. The substrates are placed vertically in a furnace and a gas including a selenide species and a carrier gas are introdu...	08/30/2011
8003535	Semiconductor device manufacturing method and target substrate processing system A semiconductor device manufacturing method includes removing copper deposits, by use of an organic acid gas and an oxidizing gas, from a surface of a second interlayer insulation film having a groove formed therein and reaching a copper-containing electric connecto...	08/23/2011
7994055	Method of manufacturing semiconductor apparatus, and semiconductor apparatus A method of manufacturing a semiconductor apparatus which includes the steps of forming a via hole and a wire trench reaching an underlying wire in an interlayer insulation film formed on the underlying wire, forming an diffusion barrier film on said underlying wire...	08/09/2011
7968464	Memory device with improved data retention The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second and into which ions from the passive layer may be provided, and from which the ions may be provid...	06/28/2011
7964506	Two step copper electroplating process with anneal for uniform across wafer deposition and void free filling on ruthenium coated wafers A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids after a post electrofill anneal. A seed-layer plating bath nucleates copper uniformly and conforma...	06/21/2011
7955980	Method of manufacturing semiconductor device A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the...	06/07/2011
7951714	High aspect ratio electroplated metal feature and method Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free f...	05/31/2011
7947602	Conductive pattern formation method The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip. ...	05/24/2011
7943517	Semiconductor device with a barrier film A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, formi...	05/17/2011
7943518	Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of th...	05/17/2011
7928011	Method for structuring a substrate using a metal mask layer formed using a galvanization process A method and intermediate product for structuring a substrate is disclosed. At least one seed layer including a first metal compound is positioned at least partially on the substrate. The seed layer is subjected to a solution comprising ions of a second metal compou...	04/19/2011
7915166	Diffusion barrier and etch stop films Films having high hermeticity and a low dielectric constant can be used as copper diffusion barrier films, etch stop films, CMP stop films and other hardmasks during IC fabrication. Hermetic films can protect the underlying layers, such as layers of metal and dielec...	03/29/2011
7892976	Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of ...	02/22/2011
7884019	Poison-free and low ULK damage integration scheme for damascene interconnects A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tr...	02/08/2011
7871929	Method of forming semiconductor devices containing metal cap layers Methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to fo...	01/18/2011
7867906	Semiconductor device and method for manufacturing same A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standa...	01/11/2011
7863194	Implantation of multiple species to address copper reliability A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the ...	01/04/2011
7858525	Fluorine-free precursors and methods for the deposition of conformal conductive films for nanointerconnect seed and fill A method including introducing a fluorine-free organometallic precursor in the presence of a substrate; and forming a conductive layer including a moiety of the organometallic precursor on the substrate according to an atomic layer or chemical vapor deposition proce...	12/28/2010
7846841	Method for forming cobalt nitride cap layers A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature fo...	12/07/2010
7838423	Method of forming capping structures on one or more material layer surfaces Methods of forming capping structures on one or more different material surfaces are provided. One embodiment includes disposing a semiconductor structure in a reduced pressure chamber, forming a capping GCIB within the reduced pressure chamber, and directing the ca...	11/23/2010
7825026	Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method A gas inlet is disposed in a lower portion of a reaction chamber, a copper substrate is disposed in an upper portion thereof, and a tungsten catalytic body heated to 1600° C. is disposed midway between the two. Ammonia gas introduced from the gas inlet is decompose...	11/02/2010
7816266	Copper diffusion barrier The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insu...	10/19/2010
7816268	Semiconductor device and manufacturing method of semiconductor device To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prev...	10/19/2010
7816267	Method for forming inlaid interconnect After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surfac...	10/19/2010
7799683	Copper interconnect wiring and method and apparatus for forming thereof Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods and apparatus for forming improved integration interconnection structures for integrated circuits by the application of ...	09/21/2010
7799684	Two step process for uniform across wafer deposition and void free filling on ruthenium coated wafers A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids. A plating bath nucleates copper uniformly and conformably at a high density in a very thin film. ...	09/21/2010

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Class 438/687 - Copper of copper alloy conductor