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| Number | Title | Issue Date |
| 8153523 | Method of etching a layer of a semiconductor device using an etchant layer A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and ... | 04/10/2012 |
| 8034716 | Semiconductor structures including vertical diode structures and methods for making the same Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium si... | 10/11/2011 |
| 7446044 | Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carb... | 11/04/2008 |
| 7407886 | Method for preparing a contact plug structure A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep tre... | 08/05/2008 |
| 7375005 | Method for reclaiming and reusing wafers Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semico... | 05/20/2008 |
| 7358561 | Source lines for NAND memory devices A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more column... | 04/15/2008 |
| 7354858 | Film formation method and apparatus for semiconductor process A film formation method for a semiconductor process is arranged to form an amorphous silicon film on a target substrate by CVD in a process field within a reaction container, while supplying a first process gas containing silicon into the process field, and setting ... | 04/08/2008 |
| 7329592 | Method for screening crystallization conditions using multifunctional substrates A method for producing crystals and for screening crystallization conditions of chemical materials on distinct metallic islands with specific functional groups by using multi-functional substrates comprising a plurality of self-assembled monolayers having at least t... | 02/12/2008 |
| 7329319 | Method for producing crystals and screening crystallization conditions A method for producing crystals and for screening crystallization conditions of chemical materials on distinct metallic islands with specific functional groups, for preparing and screening the conditions necessary to promote a specific polymorph of a crystal, and a ... | 02/12/2008 |
| 7326653 | Method of preparation of organic optoelectronic and electronic devices and devices thereby obtained A method for preparing an organic electronic or optoelectronic device is described. The method comprises depositing a layer of fluorinated polymer on a substrate, patterning the layer of fluorinated polymer to form a relief pattern and depositing from solution a lay... | 02/05/2008 |
| 7314513 | Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA a... | 01/01/2008 |
| 7304364 | Embossed mask lithography Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transpare... | 12/04/2007 |
| 7294573 | Method for controlling poly 1 thickness and uniformity in a memory array fabrication process According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surface... | 11/13/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7282417 | Ion doping method to form source and drain An ion doping method to form source and drain is disclosed. First form a gate structure and a gate spacer on a semiconductor substrate, and then use dielectric layer having trenches therein to define heavily ion-doped positions and use a Y-shaped polysilicon layer f... | 10/16/2007 |
| 7279422 | Semiconductor device with silicide film and method of manufacturing the same Provided is a semiconductor device having a suicide thin film with thermal stability and a method of manufacturing the same. The semiconductor device includes a silicon substrate containing Si a gate oxide film formed on the silicon substrate, a gate electrode conta... | 10/09/2007 |
| 7274065 | Source lines for NAND memory devices A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more column... | 09/25/2007 |
| 7271497 | Dual metal stud bumping for flip chip applications A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed t... | 09/18/2007 |
| 7268064 | Method of forming polysilicon layer in semiconductor device Disclosed herein is a method of forming a polysilicon film of a semiconductor device. Upon deposition process of a polysilicon film, the inflow of a gas is reduced to 150 sccm to 250 sccm to control abnormal deposition depending upon excessive inflow of the gas. Acc... | 09/11/2007 |
| 7256123 | Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr... | 08/14/2007 |
| 7238613 | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of a... | 07/03/2007 |
| 7229920 | Method of fabricating metal silicide layer A method of fabricating a metal silicide layer over a substrate is provided. First, a hard mask layer is formed over a gate formed on a substrate and a portion of the substrate is exposed. Thereafter, a first metal silicide layer, which is a cobalt silicide or a tit... | 06/12/2007 |
| 7226846 | Method of dry etching semiconductor substrate to reduce crystal defects in a trench A silicon oxide film (12) and a silicon nitride film (13) are sequentially formed over a silicon substrate (11) having a plane orientation (100). A trench (14) is formed with the patterned silicon nitride (13) as a mask. Argon is i... | 06/05/2007 |
| 7220672 | Semiconductor device comprising metal silicide films formed to cover gate electrode and source-drain diffusion layers and method of manufacturing the same The invention provides a semiconductor device, and a manufacturing method, comprising a semiconductor substrate, a gate insulating film, a gate electrode, and a source-drain diffusion layer. A silicide film is formed on the gate electrode and the source-drain diffus... | 05/22/2007 |
| 7220670 | Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process. ... | 05/22/2007 |
| 7208409 | Integrated circuit metal silicide method Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer i... | 04/24/2007 |
| 7205620 | Highly reliable amorphous high-k gate dielectric ZrON A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate dielectrics formed from metals such as zirconium are thermodynamically... | 04/17/2007 |
| 7202129 | Source lines for NAND memory devices A source line is formed by forming a source slot in a bulk insulation layer overlying a substrate to expose a portion of a substrate within the source slot, where the exposed portion of the substrate includes source regions of select gates associated with two or mor... | 04/10/2007 |
| 7199043 | Method of forming copper wiring in semiconductor device Disclosed in a method of forming a copper wiring in a semiconductor device. A copper layer buries a damascene pattern in which an interlayer insulating film of a low dielectric constant. The copper layer is polished by means of a chemical mechanical polishing proces... | 04/03/2007 |
| 7192892 | Atomic layer deposited dielectric layers An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing a hafnium metal layer on a substrate sur... | 03/20/2007 |
| 7183186 | Atomic layer deposited ZrTiOfilms After pulsing the second purging gas, a zirconium-containing precursor is pulsed into reaction chamber 220, at block 430. In an embodiment, the zirconium-containing precursor is ZTB. In other embodiments, a zirconium-containing precursor includes but i... | 02/27/2007 |
| 7179334 | System and method for performing semiconductor processing on substrate being processed A semiconductor process system (10) includes a measuring section (40), an information processing section (51), and a control section (52). The measuring section (40) measures a characteristic of a test target film formed on a targe... | 02/20/2007 |
| 7176402 | Method and apparatus for processing electronic parts An electronic part processing method for peeling off a resin coating of an electronic part having a terminal section. The method includes a step of irradiating, with plasma, a coated wire having copper as a principal constituent and a surface coated with a resin. | 02/13/2007 |
| 7160801 | Integrated circuit using a dual poly process A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrysta... | 01/09/2007 |
| 7144799 | Method for pre-retaining CB opening Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The L... | 12/05/2006 |
| 7135369 | Atomic layer deposited ZrAlO dielectric layers including ZrAlO An atomic layer deposited ZrAlxOy dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a zirconium-c... | 11/14/2006 |
| 7116557 | Imbedded component integrated circuit assembly and method of making same Integrated circuit components are imbedded within a laminate substrate disposed on a thermally conductive core, which provides a thermal sink. The circuit components are electrically connected to the integrated circuit via flexible electrical interconnects such as f... | 10/03/2006 |
| 7115509 | Method for forming polysilicon local interconnects Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present inventio... | 10/03/2006 |
| 7109097 | Process sequence for doped silicon fill of deep trenches A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench up... | 09/19/2006 |
| 7084078 | Atomic layer deposited lanthanide doped TiOx dielectric films A dielectric film containing atomic layer deposited lanthanide doped TiOx and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. The lantha... | 08/01/2006 |
