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| Number | Title | Issue Date |
| 4563805 | Manufacture of MOSFET with metal silicide contact Polysilicon elements of integrated circuits, for example gates (24) or interconnects, are provided with metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) ... | 01/14/1986 |
| 4551907 | Process for fabricating a semiconductor device A metal silicide interconnection technique selectively forming a metal silicide layer on a silicon layer followed by heat treating the layers so that a surface silicon dioxide layer is formed and the metal silicide layer is forced down and is buried under... | 11/12/1985 |
| 4545116 | Method of forming a titanium disilicide A method of forming a metallic silicide on silicon or polysilicon in which a masking layer such as silicon dioxide is formed on a silicon slice and patterned to expose selected areas of the slice surface. The slice is then sputter etched followed by in si... | 10/08/1985 |
| 4529619 | Ohmic contacts for hydrogenated amorphous silicon A method of forming an ohmic contact between an amorphous silicon hydride semiconductor and a substrate which includes coating a film of palladium on the substrate and overcoating the palladium with a thin film of amorphous silicon hydride forming a thin ... | 07/16/1985 |
| 4521952 | Method of making integrated circuits using metal silicide contacts A metal silicide contact to silicon devices which has broad application to almost all of the variety of silicon semiconductor devices is described. This contact with a substantial side component has particular advantage as the base contact for a bipolar t... | 06/11/1985 |
| 4507851 | Process for forming an electrical interconnection system on a semiconductor Disclosed is a process for depositing a metal film on a silicon oxide or silicon nitride surface. This process provides an extremely adherent metallic film and is resistant to interdiffusion between the semiconductor, the insulator, and the metal. The pro... | 04/02/1985 |
| 4504521 | LPCVD Deposition of tantalum silicide An improved method of forming a polycide structure is disclosed. An in-situ doped silicon layer is deposited in the amorphous state by LPCVD at 560°-580° C., a polycrystalline tantalum rich tantalum silicide layer is deposited thereover by LPCVD and the... | 03/12/1985 |
| 4502209 | Forming low-resistance contact to silicon Annealing a titanium-rich carbide film deposited on silicon produces, in a single processing step, both a stable titanium silicide contact and a titanium carbide diffusion barrier between the silicide and a subsequently formed overlying layer of aluminum.... | 03/05/1985 |
| 4495512 | Self-aligned bipolar transistor with inverted polycide base contact An inverted polycide extrinsic base contact serves as a diffusion source, yet still has low resistivity and is readily etchable down to silicon by techniques useful in manufacturing integrated circuits. The extrinsic base contact layer is made up of a met... | 01/22/1985 |
| 4477310 | Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air... | 10/16/1984 |
| 4470189 | Process for making polycide structures An improved method for making polycide structures for use in electrode and wiring interconnection applications. It includes depositing a layer of polysilicon on an insulating layer and forming on this polysilicon layer a silicide structure and a silicon c... | 09/11/1984 |
| 4462149 | Method for producing integrated MOS field effect transistors with an additional track level of metal silicides A method for producing integrated MOS field effect transistors, particularly complementary MOS field effect transistor circuits (CMOS-FET's) is provided wherein a metal silicide level, comprised preferably of tantalum silicide, is utilized as an additiona... | 07/31/1984 |
| 4444617 | Reactive ion etching of molybdenum silicide and N+ polysilicon An anisotropic etching processing for fabricating a solid state device which consists of the steps of providing a layer of silicon on the substrate and depositing a layer of molysilicide on the silicon layer. The molysilicide layer is then masked to defin... | 04/24/1984 |
| 4443930 | Manufacturing method of silicide gates and interconnects for integrated circuits A method of forming on a substrate a layer of silicon-rich metal silicide such as tungsten silicide, WSix where x>2 by cosputtering a tungsten disilicide (WSi2) target and a doped silicon target on to the substrate which is maintaine... | 04/24/1984 |
| 4411734 | Etching of tantalum silicide/doped polysilicon structures A method of forming and anisotropically etching a structure on a substrate, said structure being comprised of a layer of doped polycrystalline silicon having thereover a layer of tantalum silicide. The method comprises providing a layer of polycrystalline... | 10/25/1983 |
| 4398341 | Method of fabricating a highly conductive structure An improved method of fabricating a silicide structure includes depositing a metal, e.g., molybdenum or tungsten, directly onto a thin insulating layer of silicon dioxide and/or silicon nitride formed on a semiconductor substrate, co-depositing the metal ... | 08/16/1983 |
| 4392150 | MOS Integrated circuit having refractory metal or metal silicide interconnect layer A partial silicide layer under a polycrystalline silicon (polysi) first level interconnect reduces the sheet resistance of the first level interconnect. The polysi insulates the silicide from possibly reactive materials and gases. Since the silicide is no... | 07/05/1983 |
| 4389257 | Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silic... | 06/21/1983 |
| 4378628 | Cobalt silicide metallization for semiconductor integrated circuits In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400° C. to 500° C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15... | 04/05/1983 |
| 4373251 | Method of manufacturing a semiconductor device An undoped polycrystalline silicon layer 6 is provided on an electrically insulating layer 2 at the surface 8 of a semiconductor body 1 and a metal layer 4, for example of molybdenum, is provided on layer 6. After heating to convert part of layer 3 into a... | 02/15/1983 |
| 4364166 | Semiconductor integrated circuit interconnections An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer... | 12/21/1982 |
| 4362597 | Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, ... | 12/07/1982 |
| 4361599 | Method of forming plasma etched semiconductor contacts In the fabrication of semiconductor devices it has been found useful to employ plasma etching to create contact holes in the insulating layers that cover the wafers being processed. In particular, when wafers are being fabricated that employ small diamete... | 11/30/1982 |
| 4356622 | Method of producing low-resistance diffused regions in IC MOS semiconductor circuits in silicon-gate technology metal silicide layer formation Low-resistance diffused regions useful as current-supply paths in IC MOS semiconductor circuits in silicon-gate technology are produced by forming a metal silicide on a doped polysilicon layer positioned on a substrate, applying a SiO2 layer ov... | 11/02/1982 |
| 4329706 | Doped polysilicon silicide semiconductor integrated circuit interconnections An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer... | 05/11/1982 |
| 4322453 | Conductivity WSi2 (tungsten silicide) films by Pt preanneal layering A highly conductive layer utilizing a layer of Pt in conjunction with sputter deposited or co-evaporated WSi2 to enahnce the conductivity increase of the WSi2 layer occuring during annealing. The Pt layer is deposited as a thin layer... | 03/30/1982 |
| 4321283 | Nickel plating method A simple method for plating nickel onto silicon which renders unnecessary any catalyzing pretreatment of the silicon surface which is to receive the nickel. The method comprises the immersion of a silicon substrate in a suitable nickel bath in order that ... | 03/23/1982 |
| 4297393 | Method of applying thin metal deposits to a substrate A method of applying thin metal sensitizing deposits to the exposed silicon areas of a silicon substrate having areas of exposed silicon and silicon oxide, including the steps of immersing the silicon substrate in a basic, aqueous solution containing a me... | 10/27/1981 |
| 4290188 | Process for producing bipolar semiconductor device utilizing predeposition of dopant and a polycrystalline silicon-gold film followed by simultaneous diffusion A process for manufacturing a bipolar semiconductor device. An epitaxial layer is formed on a silicon wafer, and a base layer is formed by the diffusion of impurities having one conductivity type in a part of the epitaxial layer. Impurities having the opp... | 09/22/1981 |
| 4263058 | Composite conductive structures in integrated circuits and method of making same A composite conductive structure in integrated circuit devices is described. The composite conductive structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide. A layer... | 04/21/1981 |
| 4227944 | Methods of making composite conductive structures in integrated circuits A method of making a composite conductive structure is described. The structure includes an insulating substrate on which is provided a conductor of a refractory metal substantially nonreactive with silicon dioxide covered by a layer of a silicide of the ... | 10/14/1980 |
| 4215156 | Method for fabricating tantalum semiconductor contacts A silicon semiconductor device having contacts which include tantalum. The tantalum is useful in particular for fabricating Schottky barrier diodes having a low barrier height. The method includes: precleaning the silicon substrate prior to depositing the... | 07/29/1980 |
| 4128670 | Fabrication method for integrated circuits with polysilicon lines having low sheet resistance A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the met... | 12/05/1978 |
| 4109372 | Method for making an insulated gate field effect transistor utilizing a silicon gate and silicide interconnection vias The invention disclosed pertains to a method for the manufacture of an integrated insulated gate field effect transistor semiconductor device wherein a silicon gate structure is simultaneously formed with a composite layer of silicon and a conductive sili... | 08/29/1978 |
| 3943621 | Semiconductor device and method of manufacture therefor A semiconductor device and method of manufacture therefor includes the establishment of at least one PN junction in a semiconductor chip through conventional techniques. Electrical contacts are formed. The entire semiconductor device is coated with a pass... | 03/16/1976 |
