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| Number | Title | Issue Date |
| 7354854 | Nickel silicide method and structure Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it after a nickel layer has been deposited on the source, drain, and gate, with no cap la... | 04/08/2008 |
| 7351663 | Removing whisker defects A method of removing a defect from a gate stack on a substrate, comprises treating the gate stack with a plasma. The plasma comprises fluorine, the gate stack comprises a gate layer and a metallic layer, and substantially no photoresist is present on the substrate. | 04/01/2008 |
| 7348273 | Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device that can inhibit transformation of an NiSi layer into a disilicide is to be provided. An NiSi layer is formed on gate electrodes and source/drain regions in both of a P-MOS transistor and a N-MOS transistor (a silicid... | 03/25/2008 |
| 7348265 | Semiconductor device having a silicided gate electrode and method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device (100), among other possible elements, includes a gate oxide (140) located ov... | 03/25/2008 |
| 7338865 | Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first tra... | 03/04/2008 |
| 7338888 | Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, ... | 03/04/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7332420 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semicon... | 02/19/2008 |
| 7329582 | Methods for fabricating a semiconductor device, which include selectively depositing an electrically conductive material Methods are provided for fabricating a semiconductor device having an impurity doped region in a silicon substrate. The method comprises forming a metal silicide layer electrically contacting the impurity doped region and depositing a conductive layer overlying and ... | 02/12/2008 |
| 7326648 | Semiconductor device and fabrication process of forming silicide layer on a polysilicon pattern by reducing thickness of metal layer before forming silicide layer on the polysilicon pattern A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field... | 02/05/2008 |
| 7320914 | System and method for gate formation in a semiconductor device A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to f... | 01/22/2008 |
| 7320910 | Semiconductor device Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon sur... | 01/22/2008 |
| 7314796 | Methods for reducing wordline sheet resistance The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a control-gate poly layer including a first and a second poly-Si portion is deposited. a The first poly-Si portion is deposited on a semicond... | 01/01/2008 |
| 7307017 | Semiconductor devices and fabrication methods thereof Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device includes a silicon substrate, a source region and a drain region. A gate electrode is formed on the silicon substrate. Also, a metal silicide layer... | 12/11/2007 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7297626 | Process for nickel silicide Ohmic contacts to n-SiC A Ni2Si-nSiC Ohmic contact is formed by pulsed laser ablation deposition (PLD) of Ni2Si source target deposited on a n-SiC substrate or SiC substrate wafer with SiC epilayer. The Ni2Si Ohmic contact on n-SiC was rapid thermal anneale... | 11/20/2007 |
| 7294565 | Method of fabricating a wire bond pad with Ni/Au metallization A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN... | 11/13/2007 |
| 7294570 | Contact integration method A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposi... | 11/13/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7285485 | Method for forming a gate in a semiconductor, which prevents gate leaning caused by thermal processing A method for forming a gate in a semiconductor device includes the steps of: providing a substrate having active and field regions; selectively etching a portion of the active region to form a trench; forming on the substrate including the trench an amorphous conduc... | 10/23/2007 |
| 7285491 | Salicide process A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second ste... | 10/23/2007 |
| 7282443 | Methods of forming metal silicide The invention includes methods of forming metal silicide having bulk resistance of less than 30 micro-ohms-centimeter. The metal of the metal silicide can be selected from Groups 3, 4, 8, 9 and 10 of the periodic table, with an exemplary metal being titanium. An exe... | 10/16/2007 |
| 7282435 | Method of forming contact for dual liner product A method is provided of forming a contact to a semiconductor structure. A current-conducting member is formed which extends horizontally over a first portion of a semiconductor device region but not over a second portion of such semiconductor device region. A first ... | 10/16/2007 |
| 7282423 | Method of forming fet with T-shaped gate An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The t... | 10/16/2007 |
| 7271455 | Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for... | 09/18/2007 |
| 7271486 | Retarding agglomeration of Ni monosilicide using Ni alloys A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy l... | 09/18/2007 |
| 7271046 | Method of making a semiconductor device in which a bipolar transistor and a metal silicide layer are formed on a substrate A semiconductor device includes a bipolar transistor formed on a semiconductor substrate 1, in which a collector region 13 is formed on the semiconductor substrate 1; a first insulating layer 31 having a first opening 51 formed in ... | 09/18/2007 |
| 7268048 | Methods for elimination of arsenic based defects in semiconductor devices with isolation regions Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a ... | 09/11/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
| 7262103 | Method for forming a salicide in semiconductor device Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxi... | 08/28/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7256123 | Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr... | 08/14/2007 |
| 7256126 | Pitch reduction integrating formation of memory array and peripheral circuitry Methods and apparatus for providing a memory array fabrication process that concurrently forms memory array elements and peripheral circuitry. The invention relates to a method for fabricating memory arrays using a process that concurrently forms memory array elemen... | 08/14/2007 |
| 7256141 | Interface layer between dual polycrystalline silicon layers A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer o... | 08/14/2007 |
| 7253123 | Method for producing gate stack sidewall spacers A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materia... | 08/07/2007 |
| 7253521 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper in combination with diffusion barriers, rather than aluminum, to form the wi... | 08/07/2007 |
| 7250667 | Selectable open circuit and anti-fuse element An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate die... | 07/31/2007 |
| 7244668 | Methods of manufacturing semiconductor devices Methods for manufacturing semiconductor devices are disclosed. In one example, the semiconductor device has a gate and source/drain regions formed on a substrate. One example method includes introducing transition metal (Ti) source or precursor so that the introduce... | 07/17/2007 |
| 7244996 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 07/17/2007 |
| 7238612 | Methods of forming a double metal salicide layer and methods of fabricating semiconductor devices incorporating the same A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconduc... | 07/03/2007 |
